NNDK-MOD5272-KIT NetBurner Inc, NNDK-MOD5272-KIT Datasheet - Page 321

• Manufacturer Part Number: NNDK-MOD5272-KIT
• Description: KIT DEVELOP NETWORK FOR MOD5272
• Manufacturer: NetBurner Inc
• Series: ColdFire®r

Specifications of NNDK-MOD5272-KIT

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: MOD5272
• Primary Attributes: *
• Secondary Attributes: *
• Processor To Be Evaluated: MOD5272
• Interface Type: RS-232, RS-485, USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 528-1001

MOTOROLA
A byte of monitor channel data received on a certain port is put into an associated register
using the format shown in Figure 13-24. A maskable interrupt is generated when a byte is
written into any of these four registers.
13.5.13 GCI Monitor Channel Transmit Registers
All bits in these registers are read/write and are cleared on hardware or software reset.
The PnGMT registers are 16 bit register containing the control and monitor channel bits to
be transmitted for each of the four ports on the MCF5272.
A byte of monitor channel data to be transmitted on a certain port is put into an associated
register using the format shown in Figure 13-25. A maskable interrupt is generated when
this byte of data has been successfully transmitted.
Reset
Field
Addr
R/W
Figure 13-24. GCI Monitor Channel Receive Registers (P0GMR–P3GMR)
15–11
Bits
15
7–0
10
9
8
(P0GMT–P3GMT)
Name
EOM
MC
AB
—
M
—
MBAR + 0x360 (P0GMR); 0x362 (P1GMR); 0x364 (P2GMR); 0x366 (P3GMR)
Table 13-7. P0GMR–P3GMR Field Descriptions
Chapter 13. Physical Layer Interface Controller (PLIC)
Reserved, should be cleared.
End of message.
0 Default at reset.
1 Indicates to the CPU that an end-of-message condition has been recognized on
Abort.
0 Default at reset.
1 Indicates that the GCI controller has recognized an abort condition and is
Monitor change.
0 Default at reset.
1 Indicates to the CPU that the monitor channel data byte written to the respective
Monitor channel data byte.
the E bit. EOM is automatically cleared when the PnGMR register has been read
by the CPU.
acknowledging the abort. It is automatically cleared by the CPU when the
PnGMR register has been read.
PnGMR register has changed and that the data is available for processing.
Automatically cleared by the CPU when the PnGMR register has been read.
Clearing this bit by reading this register also clears the aperiodic GMR interrupt.
11
EOM
10
AB
0000_0000_1111_1111
9
Read Only
MC
8
Description
7
M
PLIC Registers
13-25
0