NNDK-MOD5272-KIT NetBurner Inc, NNDK-MOD5272-KIT Datasheet - Page 507

• Manufacturer Part Number: NNDK-MOD5272-KIT
• Description: KIT DEVELOP NETWORK FOR MOD5272
• Manufacturer: NetBurner Inc
• Series: ColdFire®r

Specifications of NNDK-MOD5272-KIT

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: MOD5272
• Primary Attributes: *
• Secondary Attributes: *
• Processor To Be Evaluated: MOD5272
• Interface Type: RS-232, RS-485, USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 528-1001

1
MOTOROLA
23.5 SDRAM Interface Timing Specifications
Table 23-10 lists SDRAM interface timings.
Figure 23-9 shows SDRAM timings listed in Table 23-10.
SD1
SD2
SD3
SD4
SD5
SD6
SD7
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
SD16
Name
All timing references to SDCLK are given to its rising edge when bit 3 of the SDRAM control register is 0.
SDCLK to address output A[22:0] valid
SDCLK to address output A[22:0] invalid (output hold)
SDCLK to DQM[3:0] valid
SDCLK to DQM[3:0] invalid (output hold)
SDCLK to data output (D[31:0]) valid (signal from driven or three-state)
SDCLK to data output (D[31:0]) invalid (output hold)
SDCLK to CAS0, RAS0, SDBA[1:0], SDCLKE, SDRAMWE, valid
SDCLK to CAS0, RAS0, SDBA[1:0], SDCLKE, SDRAMWE, invalid (output hold)
SDCLK to SDCS valid
SDCLK to SDCS invalid (output hold)
SDCLK to A10_PRECHG valid
SDCLK to A10_PRECHG invalid (output hold)
SDCLK to data output (D[31:0]) high impedance
Data input (D[31:0]) valid to SDCLK (setup) (pipeline mode, SDRAM control
register b4 = 1)
Data input (D[31:0]) valid to SDCLK (setup) (straight-through mode, SDRAM
control register b4 = 0)
SDCLK to data input (D[31:0]) invalid (hold)
Above 48 MHz, the memory bus may need to be configured for
one wait state. It is the responsibility of the user to determine
the actual frequency at which to insert a wait state since this
depends on the access time of SRAM or SDRAM used in a
particular system implementation.
Wait states are inserted for SRAM accesses by programming
bits 6–2 of the chip select option registers.
A wait state is added for SDRAM read accesses by setting bit
4 of the SDRAM control register.
Table 23-10. SDRAM Interface Timing Specifications
Chapter 23. Electrical Characteristics
Characteristic
Control Inputs
NOTE:
1
SDRAM Interface Timing Specifications
13.0
Min
1.0
1.0
1.0
5.5
—
—
—
—
—
—
—
0–66 MHz
1
1
1
0
Max
13.0
13.0
9.5
—
—
—
—
—
—
—
—
—
9
7
8
6
23-13
Unit
nS
nS
nS
nS
nS
nS
nS
nS
nS