NNDK-MOD5272-KIT NetBurner Inc, NNDK-MOD5272-KIT Datasheet - Page 223

• Manufacturer Part Number: NNDK-MOD5272-KIT
• Description: KIT DEVELOP NETWORK FOR MOD5272
• Manufacturer: NetBurner Inc
• Series: ColdFire®r

Specifications of NNDK-MOD5272-KIT

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: MOD5272
• Primary Attributes: *
• Secondary Attributes: *
• Processor To Be Evaluated: MOD5272
• Interface Type: RS-232, RS-485, USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 528-1001

MOTOROLA
10.3.3 DMA Source Address Register (DSAR)
The DSAR provides a 32-bit address, which the DMA controller drives onto the internal
address bus for all of the channel’s read accesses. The address value is altered after each
read access according to the addressing mode.
Bits
7–5
11
10
9
8
4
3
2
1
0
ASCEN Address sequence complete interrupt enable.
Name
TCEN
TEEN
ASC
INV
TC
TE
—
—
—
0 ASC interrupt is disabled.
1 ASC interrupt is enabled.
Reserved, should be cleared.
Transfer error interrupt enable.
0 TE interrupt is disabled.
1 TE interrupt is enabled.
Transfer complete interrupt enable.
0 TC interrupt is disabled.
1 TC interrupt is enabled.
Reserved, should be cleared.
Invalid combination.
0 No invalid combination detected.
1 An invalid combination of request and address modes is programmed into the mode register.
Address sequence complete.
0 Address sequence is not complete.
1 The address sequence is complete. This occurs when the byte counter decrements to 0.
Reserved, should be cleared.
Transfer error.
0 No transfer error.
1 A DMA data transfer terminated with an error such as an internally generated bus error. This
Transfer complete.
1 A data transfer completed successful. The bit is cleared when DMA module is reset. Writing a 0
INV remains set until it is cleared by writing a 1 to it or by a hardware reset. Writing a 0 has no
effect. No further transfers can take place when this bit is set.
Corresponds to DMA complete. ASC remains set until it is cleared by writing a 1 to its location
or by a hardware reset. Writing a 0 has no effect. No further transfers can take place when ASC
is set. It is important to ensure that the combination of source address, destination address, and
transfer sizes ensures that the byte counter always decrements to 0.
generally occurs when the address is not decoded successfully by an on-chip peripheral or by a
chip select register. TE remains set until it is cleared by writing a 1 to its location or by a
hardware reset. Writing 0 has no effect. No further transfers can take place when TE is set.
to this location has no effect. This bit is available to show that the DMA transfers have started.
Otherwise it is not essential to monitor the status of this bit.
Table 10-3. DIR Field Descriptions (Continued)
Chapter 10. DMA Controller
Description
DMA Controller Registers
10-5