NNDK-MOD5272-KIT NetBurner Inc, NNDK-MOD5272-KIT Datasheet - Page 27

• Manufacturer Part Number: NNDK-MOD5272-KIT
• Description: KIT DEVELOP NETWORK FOR MOD5272
• Manufacturer: NetBurner Inc
• Series: ColdFire®r

Specifications of NNDK-MOD5272-KIT

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: MOD5272
• Primary Attributes: *
• Secondary Attributes: *
• Processor To Be Evaluated: MOD5272
• Interface Type: RS-232, RS-485, USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 528-1001

Figure
Number
MOTOROLA
13-12
13-13
13-14
13-15
13-16
13-17
13-18
13-19
13-20
13-21
13-22
13-23
13-24
13-25
13-26
13-27
13-28
13-29
13-30
13-31
13-32
13-33
13-34
13-35
13-36
13-37
13-38
13-39
13-40
13-41
13-42
14-1
14-2
14-3
14-4
14-5
14-6
14-7
14-8
14-9
14-10
15-1
15-2
PLIC Clock Generator .............................................................................................. 13-13
B1 Receive Data Registers P0B1RR–P3B1RR ........................................................ 13-16
B2 Receive Data Registers P0B2RR – P3B2RR ...................................................... 13-16
D Receive Data Registers P0DRR–P3DRR ............................................................. 13-17
B1 Transmit Data Registers P0B1TR–P3B1TR ....................................................... 13-17
B2 Transmit Data Registers P0B2TR–P3B2TR ....................................................... 13-18
D Transmit Data Registers P0DTR–P3DTR ............................................................ 13-18
Port Configuration Registers (P0CR–P3CR)............................................................ 13-19
Loopback Control Register (PLCR) ......................................................................... 13-20
Interrupt Configuration Registers (P0ICR–P3ICR).................................................. 13-21
Periodic Status Registers (P0PSR–P3PSR) .............................................................. 13-22
Aperiodic Status Register (PASR)............................................................................ 13-24
GCI Monitor Channel Receive Registers (P0GMR–P3GMR) ................................. 13-25
GCI Monitor Channel Transmit Registers (P0GMT–P3GMT) ................................ 13-26
GCI Monitor Channel Transmit Abort Register (PGMTA) ..................................... 13-26
GCI Monitor Channel Transmit Status Register (PGMTS)...................................... 13-27
GCI C/I Channel Receive Registers (P0GCIR–P3GCIR) ........................................ 13-28
GCI C/I Channel Transmit Registers (P0GCIT–P3GCIT) ....................................... 13-29
GCI C/I Channel Transmit Status Register (PGCITSR)........................................... 13-30
D-Channel Status Register (PDCSR)........................................................................ 13-30
D-Channel Request Registers (PDRQR) .................................................................. 13-31
Sync Delay Registers (P0SDR–P3SDR) .................................................................. 13-32
Clock Select Register (PCSR) .................................................................................. 13-33
Port 1 Configuration Register (P1CR)...................................................................... 13-35
Port 1 Interrupt Configuration Register (P1ICR)...................................................... 13-36
ISDN SOHO PABX Example .................................................................................. 13-37
Standard IDL2 10-Bit Mode ..................................................................................... 13-38
ISDN SOHO PABX Example .................................................................................. 13-39
Standard IDL2 10-bit mode. ..................................................................................... 13-40
Two-Line Remote Access......................................................................................... 13-41
Standard IDL2 8-Bit mode........................................................................................ 13-41
QSPI Block Diagram .................................................................................................. 14-2
QSPI RAM Model ...................................................................................................... 14-5
QSPI Mode Register (QMR) ...................................................................................... 14-9
QSPI Clocking and Data Transfer Example ............................................................. 14-11
QSPI Delay Register (QDLYR)................................................................................ 14-11
QSPI Wrap Register (QWR)..................................................................................... 14-12
QSPI Interrupt Register (QIR) .................................................................................. 14-12
QSPI Address Register ............................................................................................. 14-14
QSPI Data Register ................................................................................................... 14-14
Command RAM Registers (QCR0–QCR15)............................................................ 14-15
Timer Block Diagram ................................................................................................. 15-2
Timer Mode Registers (TMR0–TMR3)...................................................................... 15-3
ILLUSTRATIONS
Illustrations
Title
Number
Page
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