NNDK-MOD5272-KIT NetBurner Inc, NNDK-MOD5272-KIT Datasheet - Page 448

• Manufacturer Part Number: NNDK-MOD5272-KIT
• Description: KIT DEVELOP NETWORK FOR MOD5272
• Manufacturer: NetBurner Inc
• Series: ColdFire®r

Specifications of NNDK-MOD5272-KIT

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: MOD5272
• Primary Attributes: *
• Secondary Attributes: *
• Processor To Be Evaluated: MOD5272
• Interface Type: RS-232, RS-485, USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 528-1001

Physical Layer Interface Controller TDM Ports and UART 1
19.16.2.3 GCI/IDL Data In (DIN1)
IDL mode: The DIN1 input is for clocking data into IDL port 1. Data is clocked into DIN1
on the falling edge of DCL1. DIN1 is also used for clocking data into ports 2 and 3.
GCI mode: The DIN1 input is for clocking data into GCI port 1. DCL1 is twice the bit rate,
that is, two clocks per data bit. DIN1 is also used for clocking data into ports 2 and 3.
19.16.2.4 GCI/IDL Frame Sync (FSC1/FSR1/DFSC1)
IDL mode: FSR1 is an input for the 8-KHz frame sync for port 1.
GCI mode: FSC1 is an input for the 8-KHz frame sync for port 1. Normally the GCI FSC
signal is two clocks wide and is aligned with the first B channel bit of the GCI frame. Many
U-interface devices including the MC145572 and MC145576 change the width of FSC to
one clock every 12 mS, indicating a U-interface super frame boundary. The MCF5272 can
accept either frame sync width.
When this pin is configured as an output, the DFSC1 sync signal from the on-chip clock
synthesizer is output on this pin. Also DFSC1 is used to internally drive the port 1 frame
sync and the delayed sync generators associated with ports 2 and 3. The width of DFSC1
can be configured for 1, 2, 8, or 16 DCL clocks duration. The location of DFSC1 is
programmable in single clock increments up to a maximum count of 0x3FF.
19.16.2.5 D-Channel Request (DREQ1/PA14)
IDL mode: This pin can be configured as the DREQ1 output in IDL mode for signalling to
a layer 1 S/T transceiver that a frame of data is ready to be sent on the port 1 D channel.
Port A mode: I/O pin PA14.
19.16.2.6 D-Channel Grant (DGNT1_INT6/PA15_INT6)
This pin can be independently configured as the input, DGNT1, used by a Layer one ISDN
S/T transceiver to indicate that D-channel access has been granted.
Port A mode: I/O pin PA15.
Special interrupt mode: The INT6 interrupt can be enabled independently of the pin being
configured for DGNT1 or PA15. This is particularly useful when configured for PA15
operation because INT6 can be used to signal a change of data on the PAx pins.
19.16.3 GCI/IDL TDM Ports 2 and 3
Physical Layer Interface port 2 is an additional GCI/IDL port. This Physical Layer Interface
shares the DIN1, DOUT1, and DCL1 pins of Physical Layer Interface port 1. The operating
mode is selected by the same register control bit that selects the operating mode for port 1.
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MCF5272 User’s Manual
MOTOROLA