NNDK-MOD5272-KIT NetBurner Inc, NNDK-MOD5272-KIT Datasheet - Page 473
NNDK-MOD5272-KIT
Manufacturer Part Number
NNDK-MOD5272-KIT
Description
KIT DEVELOP NETWORK FOR MOD5272
Manufacturer
NetBurner Inc
Series
ColdFire®r
Datasheets
1.MOD5272-100IR.pdf
(2 pages)
2.MOD5272-100IR.pdf
(550 pages)
3.NNDK-MOD5282-KIT.pdf
(2 pages)
Specifications of NNDK-MOD5272-KIT
Main Purpose
*
Embedded
*
Utilized Ic / Part
MOD5272
Primary Attributes
*
Secondary Attributes
*
Processor To Be Evaluated
MOD5272
Interface Type
RS-232, RS-485, USB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
Other names
528-1001
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MOTOROLA
longword is misaligned at an address that is not evenly divisible by four. However, because
operands can reside at any byte boundary, they can be misaligned.
Although the MCF5272 does not enforce any alignment restrictions for data operands
(including program counter (PC) relative data addressing), significant performance
degradation can occur when additional bus cycles are required for longword or word
operands that are misaligned. For maximum performance, data items should be aligned on
their natural boundaries. All instruction words and extension words must reside on word
boundaries. An address error exception occurs with any attempt to prefetch an instruction
word at an odd address.
The MCF5272 converts misaligned operand accesses to a sequence of aligned accesses.
Figure 20-18 illustrates the transfer of a longword operand from a byte address to a 32-bit
port, requiring more than one bus cycle. Figure 20-19 is similar to the example illustrated
in Figure 20-18 except that the operand is word-sized and the transfer requires only two bus
cycles.
20.9 Interrupt Cycles
All interrupt vectors are internally generated. The MCF5272 does not support external
interrupt acknowledge cycles. The System Integration Module prioritizes all interrupt
requests and issues the appropriate vector number in response to an interrupt acknowledge
cycle. Refer to the System Integration chapter for details on the interrupt vectors and their
priorities.
When an external peripheral device requires the services of the CPU, it can signal the
ColdFire core to take an interrupt exception. The external peripheral devices use the
interrupt request signals (INTx) to signal an interrupt condition to the MCF5272. The
interrupt exception transfers control to a routine that responds appropriately.
There are a total of six external interrupt inputs, INT[6:1]. Depending on the pin
configuration between three and six of these pins are available. Each interrupt input pin is
Transfer 1
Transfer 2
Transfer 3
Transfer 1
Transfer 2
Figure 20-18. Example of a Misaligned Longword Transfer
Figure 20-19. Example of a Misaligned Word Transfer
31
31
Byte 3
Byte 1
—
—
—
24 23
24 23
Chapter 20. Bus Operation
Byte 0
—
—
—
—
16 15
16 15
Byte 1
—
—
—
—
8 7
8 7
Byte 2
Byte 0
—
—
—
0
0
Interrupt Cycles
A[2:0]
A[2:0]
001
010
100
001
100
20-19
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