NNDK-MOD5272-KIT NetBurner Inc, NNDK-MOD5272-KIT Datasheet - Page 168

• Manufacturer Part Number: NNDK-MOD5272-KIT
• Description: KIT DEVELOP NETWORK FOR MOD5272
• Manufacturer: NetBurner Inc
• Series: ColdFire®r

Specifications of NNDK-MOD5272-KIT

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: MOD5272
• Primary Attributes: *
• Secondary Attributes: *
• Processor To Be Evaluated: MOD5272
• Interface Type: RS-232, RS-485, USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 528-1001

Programming Model
6.2.2 Module Base Address Register (MBAR)
The supervisor-level MBAR, Figure 6-2, specifies the base address and allowable access
types for all internal peripherals. It is written with a MOVEC instruction using the CPU
address 0xC0F. (See the ColdFire Family Programmer’s Reference Manual.) MBAR can
be read or written through the debug module as a read/write register, as described in.” Once
MBAR has been initialized, it can be read and written in supervisor mode at the address
programmed into the base address (BA) field.
The valid bit, MBAR[V], is cleared at system reset to prevent incorrect references before
MBAR is written; other MBAR bits are uninitialized at reset. To access internal peripherals,
write MBAR with the appropriate base address (BA) and set MBAR[V] after system reset.
All internal peripheral registers occupy a single relocatable memory block along 64-Kbyte
boundaries. If MBAR[V] is set, MBAR[BA] is compared to the upper 16 bits of the full
32-bit internal address to determine if an internal peripheral is being accessed. MBAR
masks specific address spaces using the address space fields. Attempts to access a masked
address space generate an external bus access.
Addresses hitting overlapping memory spaces take the following priority:
Thus, if an overlapping address hits in the SRAM, ROM, or cache, the SIM will not
generate a bus cycle, either externally or to an on-chip peripheral.
Table 6-2 describes MBAR fields.
6-4
Address
Reset
1. SRAM, ROM, and cache
2. MBAR
3. Chip select
Field
R/W
31
The MBAR region must be mapped to non-cacheable space.
Figure 6-2. Module Base Address Register (MBAR)
W initially through MOVEC; R/W after initialization in supervisor mode
BA
CPU + 0x0C0F initially; MBAR+0x000 after initialization
MCF5272 User’s Manual
NOTE:
16 15
Undefined
—
5
SC SD UC UD V
4
Attribute Mask Bits
3
MOTOROLA
2
1
0
0