HD6432646 Hitachi, HD6432646 Datasheet - Page 998

• Manufacturer Part Number: HD6432646
• Description: (HD64F264x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

LPWRCR—Low-Power Control Register
964
Direct Transition ON Flag
Note: * Always set high-speed mode when shifting to watch mode or sub-active mode.
Bit
Initial value
Read/Write
0
1
When the SLEEP instruction is executed in high-speed mode or medium-speed mode, operation shifts
When the SLEEP instruction is executed in sub-active mode, operation shifts to sub-sleep mode or
When the SLEEP instruction is executed in high-speed mode or medium-speed mode, operation shifts
When the SLEEP instruction is executed in sub-active mode, operation shifts directly to high-speed
to sleep mode, software standby mode, or watch mode*
watch mode
directly to sub-active mode*, or shifts to sleep mode or software standby mode
mode, or shifts to sub-sleep mode
Note: * Always set high-speed mode when shifting to watch mode or sub-active mode.
Low-Speed ON Flag
0
1
When the SLEEP instruction is executed in high-speed mode or medium-speed mode,
When the SLEEP instruction is executed in sub-active mode, operation shifts to watch
When the SLEEP instruction is executed in high-speed mode, operation shifts to watch
When the SLEEP instruction is executed in sub-active mode, operation shifts to sub-
Operation shifts to sub-active mode when watch mode is cancelled
operation shifts to sleep mode, software standby mode, or watch mode*
mode or shifts directly to high-speed mode
mode or sub-active mode
sleep mode or watch mode
Operation shifts to high-speed mode when watch mode is cancelled
DTON
Noise Elimination Sampling Frequency Select
R/W
0
1
7
0
Sampling using 1/32 ø
Sampling using 1/4 ø
LSON
R/W
6
0
Oscillation Circuit Feedback Resistance Control Bit
0
1
When the main clock is oscillating, sets the feedback
resistance ON. When the main clock is stopped, sets
the feedback resistance OFF
Sets the feedback resistance OFF
NESEL
R/W
5
0
SUBSTP
R/W
4
0
RFCUT
R/W
H'FDEC
3
0
Subclock Enable
0
1
Note: The clock frequency after a
Frequency Multiplication Factor
0
1
Enables subclock generation
Disables subclock generation
0
1
0
1
R/W
multiplication must not exceed
the maximum operating
frequency of this LSI.
—
2
0
Setting prohibited
1
2
4
STC1
R/W
1
0
STC0
R/W
0
0
System