HD6432646 Hitachi, HD6432646 Datasheet - Page 170

• Manufacturer Part Number: HD6432646
• Description: (HD64F264x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

2. Satisfaction of break condition
3. Interrupt handling
6.3.3
1. The PC break interrupt is shared by channels A and B. The channel from which the request
2. The CMFA and CMFB flags are not cleared to 0, so 0 must be written to CMFA or CMFB
3. A PC break interrupt generated when the DTC is the bus master is accepted after the bus has
6.3.4
The operation when a PC break interrupt is set for an instruction fetch at the address after a
SLEEP instruction is shown below.
1. When the SLEEP instruction causes a transition from high-speed (medium-speed) mode to
2. When the SLEEP instruction causes a transition from high-speed (medium-speed) mode to
3. When the SLEEP instruction causes a transition from subactive mode to high-speed (medium-
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was issued must be determined by the interrupt handler.
after first reading the flag while it is set to 1. If the flag is left set to 1, another interrupt will be
requested after interrupt handling ends.
been transferred to the CPU by the bus controller.
sleep mode, or from subactive mode to subsleep mode:
After execution of the SLEEP instruction, a transition is not made to sleep mode or subsleep
mode, and PC break interrupt handling is executed. After execution of PC break interrupt
handling, the instruction at the address after the SLEEP instruction is executed (figure 6-2
(A)).
subactive mode:
After execution of the SLEEP instruction, a transition is made to subactive mode via direct
transition exception handling. After the transition, PC break interrupt handling is executed,
then the instruction at the address after the SLEEP instruction is executed (figure 6-2 (B)).
speed) mode:
After execution of the instruction that performs a data access on the set address, a PC break
After priority determination by the interrupt controller, PC break interrupt exception
request is generated and the condition match flag (CMFA) is set.
handling is started.
Notes on PC Break Interrupt Handling
Operation in Transitions to Power-Down Modes