HD6432646 Hitachi, HD6432646 Datasheet - Page 13

• Manufacturer Part Number: HD6432646
• Description: (HD64F264x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

Section
15.3.7 Interrupt
Interface
Table 15-5 HCAN
Interrupt Sources
15.5 Usage Notes
9. HTxD pin output
in error passive state
10. Transition to
HCAN sleep mode
11. Message
transmission
cancellation (TxCR)
12. TxCR in the bus
off state
18.1.4 Register
Configuration
Table 18-2 LCD
Controller/Driver
Registers
22.6.3 Setting
Oscillation
Stabilization Time
after Clearing
Software Standby
Mode
633
Page
583
587
743
Note * 2 deleted
LCD RAM
Module stop control
register D
Description
IRR3
IRR4
IRR7
Newly added
9.
10. Transition to HCAN sleep mode
11. Message transmission cancellation (TxCR)
12. TxCR in the bus off state
Note amended
Note: * Do not use this setting.
HTxD pin output in error passive state
If the HRxD pin becomes fixed at 1 during message transmission or
reception when the HCAN is in the error active state, the HTxD pin will
output 0 continuously while in the error passive state. To stop continuous 0
output to the CAN bus, disable the HCAN by means of an error warning
interrupt or by setting the HCAN module stop mode through detection of a
fixed 1 state by the HxRD pin monitor.
The HCAN stops (transmission/reception stops) when MCR0 is cleared to 0
immediately after an HCAN sleep mode transition effected by setting TXPR
of the HCAN to 1 and setting MCR5 to 1. When a transition is made to the
HCAN sleep mode by means of the above steps, a 10-cycle wait should be
inserted after the TxPR setting. After an HCAN sleep mode transition,
release the HCAN sleep mode by clearing MCR5 to 0.
If all the following conditions are met when cancellation of a transmission
message is performed by means of TxCR of the HCAN, the TxCR or TxPR
bit indicating cancellation is not cleared even though internal transmission
is canceled.
When canceling a message using TxCR, 1 should be written continuously
until TxCR or TxPR becomes 0.
If TxPR is set before the HCAN goes to the bus off state, and a transition is
made to the bus off state with transmission incomplete, cancellation will be
performed even if TxCR is set during the bus off period, and the message
will be transmitted after a transition to the error active state.
Error warning interrupt (TEC
Error warning interrupt (REC
Overload frame transmission interrupt
—
MSTPCRD
R/W
R/W
96)
96)
Undefined
B'11******
H'FC40 to H'FC53
H'FC60