HD6432646 Hitachi, HD6432646 Datasheet - Page 1063

• Manufacturer Part Number: HD6432646
• Description: (HD64F264x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

TCSR0—Timer Control/Status Register 0
Note: * Only a 0 may be written to this bit to clear the flag.
Bit
Initial value
Read/Write
Overflow Flag
0
1
TCSR0 register differs from other registers in being more difficult to write to.
For details see section 12.2.4, Notes on Register Access.
[Clearing conditions]
[Setting condition]
When TCNT overflows (changes from H'FF to H'00)
(When internal reset request generation is selected in watchdog timer mode,
OVF is cleared automatically by the internal reset)
Cleared when 0 is written to the TME bit (Only applies to WDT1)
Cleared by reading TCSR when OVF = 1, then write 0 in OVF
Timer Mode Select
Note: * For details see section 12.2.3, Reset Control/Status Register (RSTCSR).
R/(W)*
0
1
OVF
7
0
Interval timer mode: WDT0 requests an interval timer interrupt (WOVI) from
the CPU when the TCNT overflows
Watchdog timer mode: A reset is issued when the TCNT overflows if the
RSTE bit of RSTCSR is set to 1*
Timer Enable
WT/IT
0
1
R/W
6
0
TCNT is initialized to H'00 and halted
TCNT counts
Note: * An overflow period is the time interval between the
Clock Select 2 to 0
CKS2 CKS1 CKS0
TME
R/W
0
1
5
0
start of counting up from H'00 on the TCNT and the
occurrence of a TCNT overflow.
0
1
0
1
—
—
4
1
0
1
0
1
0
1
0
1
H'FF74(W), H'FF74(R)
—
—
3
1
ø/2
ø/64
ø/128
ø/512
ø/2048
ø/8192
ø/32768
ø/131072
Clock
CKS2
R/W
2
0
(where ø = 20 MHz)
Overflow Period*
CKS1
R/W
1
0
25.6 s
819.2 s
1.6 ms
6.6 ms
26.2 ms
104.9 ms
419.4 ms
1.68 s
CKS0
R/W
0
0
WDT0
1029