HD6432646 Hitachi, HD6432646 Datasheet - Page 1016

• Manufacturer Part Number: HD6432646
• Description: (HD64F264x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

TCR3—Timer Control Register 3
982
Bit
Initial value
Read/Write
Counter Clear
Notes: *1
0
1
CCLR2
0
1
0
1
R/W
7
0
*2
0
1
0
1
0
1
0
1
Synchronous operation setting is performed by setting the
SYNC bit in TSYR to 1.
When TGRC or TGRD is used as a buffer register, TCNT is
not cleared because the buffer register setting has priority,
and compare match/input capture does not occur.
TCNT clearing disabled
TCNT cleared by TGRA compare match/input capture
TCNT cleared by TGRB compare match/input capture
TCNT cleared by counter clearing for another channel
performing synchronous clearing/synchronous operation
TCNT clearing disabled
TCNT cleared by TGRC compare match/input capture
TCNT cleared by TGRD compare match/input capture
TCNT cleared by counter clearing for another channel
performing synchronous clearing/synchronous operation
CCLR1
R/W
6
0
Note: Internal clock edge selection is valid when the input clock
Clock Edge
0
1
—
0
1
CCLR0
is ø/4 or slower. This setting is ignored if the input clock is ø/1,
or when overflow/underflow of another channel is selected.
R/W
Count at rising edge
Count at falling edge
Count at both edges
5
0
Time Prescaler
0
1
CKEG1
0
1
0
1
R/W
4
0
0
1
0
1
0
1
0
1
Internal clock: counts on ø/1
Internal clock: counts on ø/4
Internal clock: counts on ø/16
Internal clock: counts on ø/64
External clock: counts on TCLKA pin input
Internal clock: counts on ø/1024
Internal clock: counts on ø/256
Internal clock: counts on ø/4096
CKEG0
R/W
H'FE80
3
0
TPSC2
R/W
2
0
TPSC1
R/W
*2
*2
1
0
*1
*1
TPSC0
R/W
0
0
TPU3