HD6432646 Hitachi, HD6432646 Datasheet - Page 401

no-image

HD6432646

Manufacturer Part Number
HD6432646
Description
(HD64F264x Series) 16-Bit Microcomputer
Manufacturer
Hitachi
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6432646A52FCJ
Manufacturer:
RENESAS
Quantity:
1 000
Part Number:
HD6432646A52FCJ
Manufacturer:
HIT
Quantity:
1 000
Part Number:
HD6432646A52FCJ
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Part Number:
HD6432646B37FCJ
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Part Number:
HD6432646B67FCJ
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Part Number:
HD6432646B82FCJ
Manufacturer:
RENESAS
Quantity:
1 000
Part Number:
HD6432646B99FCJ
Manufacturer:
MOT
Quantity:
44
Part Number:
HD6432646B99FCJ
Manufacturer:
RENESAS
Quantity:
3 967
Part Number:
HD6432646B99FCJ
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Part Number:
HD6432646C41FCJ
Manufacturer:
RENESAS
Quantity:
1 954
Part Number:
HD6432646C41FCJ
Manufacturer:
RENESAS
Quantity:
1 700
Part Number:
HD6432646C41FCJ
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Part Number:
HD6432646C64FCJ
Manufacturer:
RENESAS
Quantity:
1 500
Part Number:
HD6432646C90FCJV
Manufacturer:
RENESAS
Quantity:
3 967
Part Number:
HD6432646D08FCJV
Manufacturer:
RENESAS
Quantity:
1 700
Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is
set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare
match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The
TPU has 16 input capture/compare match interrupts, four each for channels 0 and 3, and two each
for channels 1, 2, 4, and 5.
Overflow Interrupt: An interrupt is requested if the TCIEV bit in TIER is set to 1 when the
TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a channel. The interrupt
request is cleared by clearing the TCFV flag to 0. The TPU has six overflow interrupts, one for
each channel.
Underflow Interrupt: An interrupt is requested if the TCIEU bit in TIER is set to 1 when the
TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on a channel. The interrupt
request is cleared by clearing the TCFU flag to 0. The TPU has four underflow interrupts, one
each for channels 1, 2, 4, and 5.
10.5.2
DTC Activation: The DTC can be activated by the TGR input capture/compare match interrupt
for a channel. For details, see section 8, Data Transfer Controller (DTC).
A total of 16 TPU input capture/compare match interrupts can be used as DTC activation sources,
four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5.
10.5.3
The A/D converter can be activated by the TGRA input capture/compare match for a channel.
If the TTGE bit in TIER is set to 1 when the TGFA flag in TSR is set to 1 by the occurrence of a
TGRA input capture/compare match on a particular channel, a request to start A/D conversion is
sent to the A/D converter. If the TPU conversion start trigger has been selected on the A/D
converter side at this time, A/D conversion is started.
In the TPU, a total of six TGRA input capture/compare match interrupts can be used as A/D
converter conversion start sources, one for each channel.
DTC Activation
A/D Converter Activation
367

Related parts for HD6432646