HD6432646 Hitachi, HD6432646 Datasheet - Page 689
HD6432646
Manufacturer Part Number
HD6432646
Description
(HD64F264x Series) 16-Bit Microcomputer
Manufacturer
Hitachi
Datasheet
1.HD6432646.pdf
(1155 pages)
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19.3
When the RAME bit is set to 1, accesses to addresses H'FFE000 to H'FFEFBF and H'FFFFC0 to
H'FFFFFF in the H8S/2646, H8S/2646R, H8S/2648, and H8S/2648R to addresses H'FFE7C0 to
H'FFEFBF and H'FFFFC0 to H'FFFFFF in the H8S/2645 and H8S/2647, are directed to the on-
chip RAM. When the RAME bit is cleared to 0, the off-chip address space is accessed.
Since the on-chip RAM is connected to the CPU by an internal 16-bit data bus, it can be written to
and read in byte or word units. Each type of access can be performed in one state.
Even addresses use the upper 8 bits, and odd addresses use the lower 8 bits. Word data must start
at an even address.
19.4
When Using the DTC: DTC register information can be located in addresses H'FFEBC0 to
H'FFEFBF. When the DTC is used, the RAME bit must not be cleared to 0.
Reserved Areas: Addresses H'FFB000 to H'FFDFFF in the H8S/2646, H8S/2646R, H8S/2648,
and H8S/2648R and addresses H'FFB000 to H'FFE7BF in the H8S/2645 and H8S/2647 are
reserved areas that cannot be read or written to. When the RAME bit is cleared to 0, the off-chip
address space is accessed.
Operation
Usage Notes
655
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