HD6432646 Hitachi, HD6432646 Datasheet - Page 163

• Manufacturer Part Number: HD6432646
• Description: (HD64F264x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

6.1
The PC break controller (PBC) provides functions that simplify program debugging. Using these
functions, it is easy to create a self-monitoring debugger, enabling programs to be debugged with
the chip alone, without using an in-circuit emulator. Four break conditions can be set in the PBC:
instruction fetch, data read, data write, and data read/write.
6.1.1
The PC break controller has the following features:
Two break channels (A and B)
The following can be set as break compare conditions:
The timing of PC break exception handling after the occurrence of a break condition is as
follows:
Module stop mode can be set
24 address bits
Bus cycle
Bus master
Immediately before execution of the instruction fetched at the set address (instruction fetch)
Immediately after execution of the instruction that accesses data at the set address (data
The initial setting is for PBC operation to be halted. Register access is enabled by clearing
Bit masking possible
Instruction fetch
Data access: data read, data write, data read/write
Either CPU or CPU/DTC can be selected
access)
module stop mode.
Overview
Features
Section 6 PC Break Controller (PBC)
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