HD6432646 Hitachi, HD6432646 Datasheet - Page 166

• Manufacturer Part Number: HD6432646
• Description: (HD64F264x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

6.2.2
BARB is the channel B break address register. The bit configuration is the same as for BARA.
6.2.3
BCRA is an 8-bit readable/writable register that controls channel A PC breaks. BCRA (1) selects
the break condition bus master, (2) specifies bits subject to address comparison masking, and (3)
specifies whether the break condition is applied to an instruction fetch or a data access. It also
contains a condition match flag.
BCRA is initialized to H'00 by a reset and in hardware standby mode.
Bit 7—Condition Match Flag A (CMFA): Set to 1 when a break condition set for channel A is
satisfied. This flag is not cleared to 0.
Bit 7
CMFA
0
1
Bit 6—CPU Cycle/DTC Cycle Select A (CDA): Selects the channel A break condition bus
master.
Bit 6
CDA
0
1
132
Bit
Initial value
Read/Write
Break Address Register B (BARB)
Break Control Register A (BCRA)
Note:* Only a 0 may be written to this bit to clear the flag.
Description
[Clearing condition]
When 0 is written to CMFA after reading CMFA = 1
[Setting condition]
When a condition set for channel A is satisfied
Description
PC break is performed when CPU is bus master
PC break is performed when CPU or DTC is bus master
R/(W)*
CMFA
0
7
CDA
R/W
6
0
BAMRA2
R/W
0
5
BAMRA1
R/W
4
0
BAMRA0
R/W
3
0
CSELA1
R/W
2
0
CSELA0
R/W
1
0
(Initial value)
(Initial value)
BIEA
R/W
0
0