HD6432646 Hitachi, HD6432646 Datasheet - Page 607

• Manufacturer Part Number: HD6432646
• Description: (HD64F264x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

When b is selected, if a number of messages are designated as waiting for transmission (TXPR
= 1), the message with the highest priority set in the message identifier (MCx[5]–MCx[8]) is
stored in the transmit buffer. CAN bus arbitration is then carried out for the message in the
transmit buffer, and message transmission is performed when the transmission right is
acquired. When the TXPR bit is set, internal arbitration is performed again, the highest-priority
message is found and stored in the transmit buffer, CAN bus arbitration is carried out in the
same way, and message transmission is performed when the transmission right is acquired.
Message transmission completion and interrupt
When a message is transmitted error-free using the above procedure, The corresponding
acknowledge bit (TXACK1–TXACK15) in the transmit acknowledge register (TXACK) and
transmit wait bit (TXPR1–TXPR15) in the transmit wait register (TXPR) are automatically
initialized. When the corresponding bits (MBIMR1 to MBIMR15) of the mailbox interrupt
mask register (MBIMR) and the mailbox empty interrupt (IRR8) of the interrupt mask register
(IMR) are set to enable interrupts, they can issue an interrupt to the CPU.
Message transmission cancellation
Transmission cancellation can be specified for a message stored in a mailbox as a transmit wait
message. A transmit wait message is canceled by setting the bit for the corresponding mailbox
(TXCR1–TXCR15) to 1 in the transmit cancel register (TXCR). When cancellation is
executed, the transmit wait register (TXPR) is automatically reset, and the corresponding bit is
set to 1 in the abort acknowledge register (ABACK). An interrupt to the CPU can be requested.
Also, if the mailbox empty interrupt (IRR8) is enabled for the bits (MBIMR1-MBIMR15)
corresponding to the mailbox interrupt mask register (MBIMR) and interrupt mask register
(IMR), interrupts may be sent to the CPU.
However, a transmit wait message cannot be canceled at the following times:
a. During internal arbitration or CAN bus arbitration
b. During data frame or remote frame transmission
Also, transmission cannot be canceled by clearing the transmit wait register (TXPR). Figure
15-8 shows a flowchart of transmit message cancellation.
Message retransmission
If transmission of a transmit message is aborted in the following cases, the message is
retransmitted automatically:
a. CAN bus arbitration failure (failure to acquire the bus)
b. Error during transmission (bit error, stuff error, CRC error, frame error, ACK error)
573