LM3S101-CRN20-XNPP ETC1 [List of Unclassifed Manufacturers], LM3S101-CRN20-XNPP Datasheet - Page 91

• Manufacturer Part Number: LM3S101-CRN20-XNPP
• Description: Microcontroller
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

Internal Memory
91
Reset
Reset
Type
Type
Bit/Field
Flash Controller Interrupt Mask (FCIM)
Offset 0x010
RO
RO
31
15
0
0
31:2
1
0
Register 8: Flash Controller Interrupt Mask (FCIM), offset 0x010
This register controls whether the flash controller generates interrupts to the controller.
RO
RO
30
14
0
0
reserved
PMASK
AMASK
Name
RO
RO
29
13
0
0
RO
RO
28
12
0
0
Type
R/W
R/W
RO
RO
RO
27
11
0
0
RO
RO
26
10
0
0
Reset
RO
RO
25
0
9
0
0
0
0
Preliminary
reserved
RO
RO
24
0
8
0
reserved
Description
Reserved bits return an indeterminate value, and should
never be changed.
Programming Interrupt Mask
This bit controls the reporting of the programming raw
interrupt status to the controller. If set, a programming-
generated interrupt is promoted to the controller. Otherwise,
interrupts are recorded but suppressed from the controller.
Access Interrupt Mask
This bit controls the reporting of the access raw interrupt
status to the controller. If set, an access-generated interrupt
is promoted to the controller. Otherwise, interrupts are
recorded but suppressed from the controller.
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
RO
RO
19
0
3
0
RO
RO
18
0
2
0
March 22, 2006
PMASK
RO
R/W
17
0
1
0
AMASK
R/W
RO
16
0
0
0