LM3S101-CRN20-XNPP ETC1 [List of Unclassifed Manufacturers], LM3S101-CRN20-XNPP Datasheet
LM3S101-CRN20-XNPP
Related parts for LM3S101-CRN20-XNPP
LM3S101-CRN20-XNPP Summary of contents
Page 1
... DS -LM3S 101- 00 LM3S101 Microcontroller C opyr ight © 2006 Lumi nary Micro , Inc DATA SHEET ...
Page 2
... United States and other countries. ARM and Thumb are registered trademarks, and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the property of others. Luminary Micro, Inc. 2499 South Capital of Texas Hwy, Suite A-100 Austin, TX 78746 Main: +1-512-279-8800 Fax: +1-512-279-8879 http://www.luminarymicro.com March 22, 2006 Preliminary LM3S101 Data Sheet 2 ...
Page 3
Table of Contents Legal Disclaimers and Trademark Information.............................................................................. 2 Revision History ............................................................................................................................. 12 About This Document..................................................................................................................... 13 Audience........................................................................................................................................................... 13 About This Manual............................................................................................................................................ 13 Related Documents .......................................................................................................................................... 13 Documentation Conventions............................................................................................................................. 13 1. Architectural Overview............................................................................................................ 16 1.1 Product Features ...................................................................................................................................... 16 1.2 ...
Page 4
... Functional Description ............................................................................................................................ 251 13.3 Register Map........................................................................................................................................... 254 13.4 Register Descriptions .............................................................................................................................. 254 14. Pin Diagram............................................................................................................................ 262 15. Signal Tables.......................................................................................................................... 263 16. Operating Characteristics..................................................................................................... 270 17. Electrical Characteristics...................................................................................................... 271 17.1 DC Characteristics .................................................................................................................................. 271 17.2 AC Characteristics .................................................................................................................................. 273 18. Package Information ............................................................................................................. 282 Contact Information...................................................................................................................... 283 Ordering Information ....................................................................................................................................... 283 Development Kit ............................................................................................................................................. 283 March 22, 2006 Preliminary LM3S101 Data Sheet 4 ...
Page 5
List of Figures Figure 1-1. Stellaris High-Level Block Diagram ........................................................................................... 20 Figure 1-2. Stellaris System-Level Block Diagram....................................................................................... 25 Figure 2-1. CPU High-Level Block Diagram ............................................................................................... 27 Figure 2-2. TPIU Block Diagram .................................................................................................................. 28 Figure 5-1. JTAG Module Block Diagram .................................................................................................... ...
Page 6
... Figure 17-8. External Reset Timing (RST)................................................................................................... 280 Figure 17-9. Power-On Reset Timing .......................................................................................................... 280 Figure 17-10. Brown-Out Reset Timing ......................................................................................................... 280 Figure 17-11. Software Reset Timing ............................................................................................................ 281 Figure 17-12. Watchdog Reset Timing .......................................................................................................... 281 Figure 17-13. LDO Reset Timing ................................................................................................................... 281 Figure 18-1. 28-Pin SOIC ............................................................................................................................ 282 March 22, 2006 Preliminary LM3S101 Data Sheet 6 ...
Page 7
List of Tables Table 0-1. Documentation Conventions ..................................................................................................... 13 Table 3-1. Memory Map.............................................................................................................................. 29 Table 4-1. Exception Types ........................................................................................................................ 31 Table 4-2. Interrupts ................................................................................................................................... 32 Table 5-1. JTAG Port Pins Reset State ...................................................................................................... 36 Table 5-2. JTAG Instruction Register Commands ...
Page 8
... GPIO Data (GPIODATA), offset 0x000................................................................................. 100 Register 2: GPIO Direction (GPIODIR), offset 0x400.............................................................................. 101 Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 ...................................................................... 102 Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................... 103 Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C .................................................................... 104 March 22, 2006 Preliminary LM3S101 Data Sheet 8 ...
Page 9
Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 ....................................................................... 105 Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................... 106 Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ..................................................... 107 Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C ...
Page 10
... SSI Control 1 (SSICR1), offset 0x004................................................................................... 231 Register 3: SSI Data (SSIDR), offset 0x008............................................................................................ 232 Register 4: SSI Status (SSISR), offset 0x00C......................................................................................... 233 Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 ...................................................................... 234 Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ............................................................................. 235 March 22, 2006 Preliminary LM3S101 Data Sheet 10 ...
Page 11
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018.................................................................. 236 Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................... 237 Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ........................................................................... 238 Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ...
Page 12
... Revision History This table provides a summary of the document revisions. Date Revision March 2006 00 March 22, 2006 Description Initial public release. Preliminary LM3S101 Data Sheet 12 ...
Page 13
... About This Document This data sheet provides reference information for the LM3S101 microcontroller, describing the functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3 core. Audience This manual is intended for system software developers, hardware designers, and application developers ...
Page 14
... True state. For active High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNAL and SIGNAL below). Preliminary LM3S101 Data Sheet 14 ...
Page 15
Table 0-1. Documentation Conventions Notation deassert a signal SIGNAL SIGNAL Numbers Meaning Change the value of the signal from the logically True state to the logically False state. Signal names are in uppercase and in the Courier ...
Page 16
... These pioneering parts deliver customers 32-bit performance at a cost equivalent to legacy 8- and 16-bit devices, all in a package with a small footprint. The LM3S101 controller in the Stellaris family offers the advantages of ARM’s widely available development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community. Additionally, the controller uses ARM’ ...
Page 17
Architectural Overview • General-purpose timer function with an 8-bit prescaler • Programmable one-shot timer • Programmable periodic timer • User-enabled stalling when the controller asserts CPU Halt flag during debug – 16-bit Input Capture modes: • Input edge count capture ...
Page 18
... IEEE 1149.1-1990 compliant Test Access Port (TAP) controller – Debug access via JTAG and Serial Wire interfaces – Full JTAG boundary scan Package – 28-pin RoHS-compliant SOIC – Commercial and industrial operating temperatures March 22, 2006 Preliminary LM3S101 Data Sheet 18 ...
Page 19
Architectural Overview 1.2 Target Applications Factory automation and control Industrial control power devices Building and home automation 19 Preliminary March 22, 2006 ...
Page 20
... Nested Vectored Interrupt Controller (NVIC)) ICode bus LMI JTAG Test Access Port APB Bridge SRAM (TAP) Controller General-Purpose General-Purpose Input/Outputs (GPIOs) Watchdog Universal Asynchronous Synchronous Receiver/ Transmitter (UART) Comparators Preliminary LM3S101 Data Sheet Flash Timers Timer Serial Interface (SSI) Analog 20 ...
Page 21
... Pulse Width Modulation (PWM powerful technique often used to regulate a voltage by holding the frequency constant and varying the pulse width. On the LM3S101, PWM motion control functionality can be achieved through the motion control features of the general-purpose timers (using the CCP pins). The General-Purpose Timer Module’s CCP (Capture Compare PWM) pins are software programmable to support a simple PWM mode with a software-programmable output inversion of the PWM signal ...
Page 22
... The LM3S101 controller provides two independent integrated analog comparators that can be configured to drive an output or generate an interrupt. A comparator can compare a test voltage against any one of these voltages: An individual external reference voltage A shared single external reference voltage A shared internal reference voltage The comparator can provide its output to a device pin, acting as a replacement for an analog comparator on the board can be used to signal the application via interrupts to cause it to start capturing a sample sequence ...
Page 23
... Programmable GPIOs (Section 8 on page 93) General-purpose input/output (GPIO) pins offer flexibility for a variety of connections. The LM3S101 controller GPIO module is composed of three physical GPIO blocks, each corresponding to an individual GPIO port. The GPIO module is FiRM-compliant (compliant to the ARM Foundation IP for Real-Time Microcontrollers specification) and supports programmable input/output pins ...
Page 24
... Flash (Section 7.2.2 on page 81) The LM3S101 Flash controller supports flash memory. The flash is organized as a set of 1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the block to be reset to all 1s. These blocks are paired into a set of 2-KB blocks that can be individually protected ...
Page 25
... Stellaris System-Level Block Diagram VDD_3.3V LDO GND OSC0 OSC1 RST PA5/SSITx PA4/SSIRx PA3/SSIFss PA2/SSIClk PA1/U0Tx PA0/U0Rx PC3/TDO/SWO PC2/TDI PC1/TMS/SWDIO PC0/TCK/SWCLK LM3S101 LM3S101 25 LDO VDD_2.5V ARM Cortex-M3 (20 MHz) CM3Core DCode ICode NVIC Debug Bus BOSC PLL SRAM APB Bridge (2 KB) POR BOR ...
Page 26
... For more information on the ARM Cortex-M3 processor core, see the ARM® Cortex™-M3 Technical Reference Manual. For information on SWJ-DP, see the CoreSight™ Design Kit Technical Reference Manual. March 22, 2006 Preliminary LM3S101 Data Sheet 26 ...
Page 27
ARM Cortex-M3 Processor Core 2.1 Block Diagram Figure 2-1. CPU High-Level Block Diagram Vectored Interrupt Controller Serial Wire JTAG Debug Port 2.2 Functional Description Important: The ARM® Cortex™-M3 Technical Reference Manual describes all the features of an ARM Cortex-M3 in ...
Page 28
... ROM Table The default ROM table was implemented as described in the ARM® Cortex™-M3 Technical Reference Manual. 2.2.5 Memory Protection Unit (MPU) The LM3S101 controller does not include the memory protection unit (MPU) of the ARM Cortex- M3. 2.2.6 Nested Vectored Interrupt Controller (NVIC) 2.2.6.1 Interrupts The ARM® ...
Page 29
... Memory Map The memory map for the LM3S101 is provided in Table 3-1. In this manual, register addresses are given as a hexadecimal increment, relative to the module’s base address as shown in the memory map. See also Chapter 4, “Memory Map” in the ARM® Cortex™-M3 Technical Reference Manual. ...
Page 30
... Data Watchpoint and Trace (DWT) Flash Patch and Breakpoint (FPB) Reserved Nested Vectored Interrupt Controller (NVIC) Reserved Trace Port Interface Unit (TPIU) Reserved Reserved Reserved for vendor peripherals Preliminary LM3S101 Data Sheet For details on registers, see ... page 140 - - page 254 - page 83 page 51 ...
Page 31
Interrupts 4 Interrupts The ARM Cortex-M3 processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. All exceptions are handled in Handler Mode. The processor state is automatically stored to the stack on an exception, and automatically ...
Page 32
... Asserted from outside the ARM Cortex-M3 core and above fed through the NVIC (prioritized). These are all asynchronous. Table 4-2 lists the interrupts on the LM3S101 controller. Description GPIO Port A GPIO Port B GPIO Port C Reserved UART0 Reserved SSI Reserved Watchdog timer Timer0a Timer0b Timer1a Timer1b Preliminary LM3S101 Data Sheet 32 ...
Page 33
Interrupts Table 4-2. Interrupts Interrupt (Bit in Interrupt Registers) 23- 30-31 33 Description Reserved Analog Comparator 0 Analog Comparator 1 Reserved System Control Flash Control Reserved Preliminary March 22, 2006 ...
Page 34
... INTEST instruction ARM additional instructions: – APACC instruction – DPACC instruction – ABORT instruction Integrated ARM Serial Wire Debug (SWD) See the ARM® Cortex™-M3 Technical Reference Manual for more information on the ARM JTAG controller. March 22, 2006 Preliminary LM3S101 Data Sheet 34 ...
Page 35
JTAG Interface 5.1 Block Diagram Figure 5-1. JTAG Module Block Diagram TRST TAP Controller TCK TMS TDI Instruction Register (IR) BYPASS Data Register Boundary Scan Data Register IDCODE Data Register ABORT Data Register DPACC Data Register APACC Data Register 5.2 ...
Page 36
... TRST. The JTAG Test Access Port state machine can be seen in its entirety in Figure 5-2. March 22, 2006 Data Internal Internal Pull-Up Pull-Down Input Enabled Disabled Input Enabled Disabled Input Enabled Disabled Input Enabled Disabled Output Enabled Disabled Preliminary LM3S101 Data Sheet Drive Drive Value Strength N/A N/A N/A N/A N/A N/A N/A N/A 2-mA driver High-Z 36 ...
Page 37
JTAG Interface By default, the internal pull-up resistor on the TMS pin is enabled after reset. Changes to the pull- up resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled on PC1/TMS; otherwise JTAG ...
Page 38
... March 22, 2006 Select DR Scan Capture Shift Exit Pause Exit Update Preliminary LM3S101 Data Sheet Select IR Scan 1 0 Capture Shift Exit Pause Exit Update ...
Page 39
JTAG Interface 5.2.4.1 GPIO Functionality Caution – If the JTAG pins will be used as GPIOs possible to create a software sequence that prevents the debugger from connecting to the Stellaris microcontroller. If the program code loaded into ...
Page 40
... Shifts data into and out of the ARM AC Access register. Loads manufacturing information defined by the IEEE Standard 1149.1 into the IDCODE chain and shifts it out. Connects TDI to TDO through a single shift register chain. Defaults to the BYPASS instruction to ensure that TDI is always connected to TDO. Preliminary LM3S101 Data Sheet 40 ...
Page 41
JTAG Interface 5.3.1.3 SAMPLE/PRELOAD Instruction The SAMPLE/PRELOAD instruction connects the Boundary Scan data register chain between TDI and TDO. This instruction samples the current state of the pad pins for observation and preloads new test data. Each GPIO pad has ...
Page 42
... GPIO pins, the controller reset pin, RST, is included in the chain. Because the reset pin is always an input, only the input signal is included in the data register chain. March 22, 2006 12 11 Part Number 0 TDI TDO 0 Preliminary LM3S101 Data Sheet 1 0 TDO Manufacturer ...
Page 43
JTAG Interface When the Boundary Scan data register is accessed with the SAMPLE/PRELOAD instruction, the input, output, and output enable from each digital pad are sampled and then shifted out of the chain to be verified. The sampling of these ...
Page 44
... After RST is de-assserted, the main crystal oscillator must be allowed to settle and there is an internal main oscillator counter that takes from 15- account for this. During this time, internal reset to the rest of the controller is held active. March 22, 2006 Preliminary LM3S101 Data Sheet 44 ...
Page 45
System Control 3. The internal reset is released and the controller fetches and loads the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. The external reset timing is ...
Page 46
... The watchdog timer reset sequence is as follows: 1. The watchdog timer times out for the second time without being serviced internal reset is asserted. March 22, 2006 , an internal BOR condition is set. BTH Preliminary LM3S101 Data Sheet 46 ...
Page 47
System Control 3. The internal reset is released and the controller fetches and loads the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. The watchdog reset timing is ...
Page 48
... March 22, 2006 PLL (200MHz output ) OSCSRC OEN BYPASS a XTAL a PWRDN 1%; non-exact values are fine, if tolerated by the system. The ± requirement. The counter is clocked by the boot READY READY Preliminary LM3S101 Data Sheet a USESYS System Clock a SYSDIV condition is met after one of the two 48 ...
Page 49
System Control changes above the user's responsibility to have a stable clock source (like the main oscillator) before the RCC register is switched to use the PLL. 6.1.4.5 Clock Verification Timers There are three identical clock verification circuits ...
Page 50
... Sleep-Mode Clock Gating Control 1 R/W Sleep-Mode Clock Gating Control 2 R/W Deep-Sleep-Mode Clock Gating Control 0 R/W Deep-Sleep-Mode Clock Gating Control 1 R/W Deep-Sleep-Mode Clock Gating Control 2 R/W Clock verification clear R/W Allow unregulated LDO to reset the part Preliminary LM3S101 Data Sheet See page ...
Page 51
System Control 6.3 Register Descriptions The remainder of this section lists and describes the System Control registers, in numerical order by address offset. 51 Preliminary March 22, 2006 ...
Page 52
... This field is numeric and is encoded as follows changes. Major revision was most recent update. 1: One interconnect change made since last major revision update. 2: Two interconnect changes made since last major revision update. and so on. Preliminary LM3S101 Data Sheet reserved RO ...
Page 53
... The 0x00 value indicates the Stellaris family of microcontrollers. RO 0x01 Part Number This field provides the part number of the device within the family. The 0x01 value indicates the LM3S101 microcontroller Reserved bits return an indeterminate value, and should never be changed. RO see table Temperature Range This field specifies the temperature rating of the device ...
Page 54
... Bit/Field Name Type 1:0 QUAL March 22, 2006 Reset Description RO see table This field specifies the qualification status of the device. This field is encoded as follows: QUAL Preliminary LM3S101 Data Sheet Description Engineering Sample (unqualified) Pilot Production (unqualified) Fully Qualified Reserved 54 ...
Page 55
System Control Register 3: Device Capabilities 0 (DC0), offset 0x008 This register is predefined by the part and can be used to verify features. Device Capabilities Register 0 (DC0) Offset 0x008 Type ...
Page 56
... this field indicates the presence of the ARM Serial Wire Output (SWO) trace port capabilities this field indicates the presence of the ARM Serial Wire Debug (SWD) capabilities this field indicates the presence of a JTAG port. Preliminary LM3S101 Data Sheet ...
Page 57
System Control Register 5: Device Capabilities 2 (DC2), offset 0x014 This register is predefined by the part and can be used to verify features. It also acts as a mask for write operations to the Run-Mode Clock Gating Control 1 ...
Page 58
... this field indicates the presence of the C0o pin this field indicates the presence of the C0+ pin this field indicates the presence of the C0- pin Reserved bits return an indeterminate value, and should never be changed. Preliminary LM3S101 Data Sheet reserved ...
Page 59
System Control Register 7: Device Capabilities 4 (DC4), offset 0x01C This register is predefined by the part and can be used to verify features. It also acts as a mask for write operations to the Run-Mode Clock Gating Control 2 ...
Page 60
... BOR condition interrupt or reset. If the BOR resample is deasserted, the cause of the initial assertion was likely noise and the interrupt or reset is suppressed. If BORWT is 0, BOR assertions do not resample the output and any condition is reported immediately if enabled. Preliminary LM3S101 Data Sheet ...
Page 61
System Control Register 9: LDO Power Control (LDOPCTL), offset 0x034 The VADJ field in this register adjusts the on-chip output voltage (V LDO Power Control (LDOPCTL) Offset 0x034 Type Reset 0 0 ...
Page 62
... Reset Description RO 0 Reserved bits return an indeterminate value, and should never be changed. 0 Reset control for the Watchdog unit Read as 0. Preliminary LM3S101 Data Sheet R WDT ...
Page 63
System Control Register 11: Software Reset Control 1 (SRCR1), offset 0x044 Writes to this register are masked by the bits in the Device Capabilities 2 (DC2) register (see page 57). Software Reset Control 1 (DC1) Offset 0x044 ...
Page 64
... Reset Description RO 0 Reserved bits return an indeterminate value, and should never be changed. 0 Reset control for GPIO Port C. 0 Reset control for GPIO Port B. 0 Reset control for GPIO Port A. Preliminary LM3S101 Data Sheet ...
Page 65
System Control Register 13: Raw Interrupt Status (RIS), offset 0x050 Central location for system control raw interrupts. These are set and cleared by hardware. Raw Interrupt Status (RIS) Offset 0x050 Type Reset ...
Page 66
... MOFRIS is set; otherwise, an interrupt is not generated. 0 LDO Power Unregulated Interrupt Mask This bit specifies whether an LDO unregulated power situation is promoted to a controller interrupt. If set, an interrupt is generated if LDORIS is set; otherwise, an interrupt is not generated. Preliminary LM3S101 Data Sheet ...
Page 67
System Control Bit/Field Name Type 1 BORIM R/W 0 PLLFIM R/W 67 Reset Description 0 Brown-Out Reset Interrupt Mask This bit specifies whether a brown-out condition is promoted to a controller interrupt. If set, an interrupt is generated if BORRIS ...
Page 68
... BORIOR bit in the PBORCTL register is cleared. The interrupt is cleared by writing this bit. 0 PLL Fault Masked Interrupt Status This bit is set if a PLL fault is detected (stops oscillating). The interrupt is cleared by writing this bit. Preliminary LM3S101 Data Sheet ...
Page 69
System Control Register 16: Reset Cause (RESC), offset 0x05C This field specifies the cause of the reset event to software. The reset value is determined by the cause of the reset. When an external reset is the cause (EXT is ...
Page 70
... The RCGCn registers are always used to control the clocks in Run mode. This allows peripherals to consume less power when the controller sleep mode and the peripheral is unused. Preliminary LM3S101 Data Sheet reserved ...
Page 71
System Control Bit/Field Name 26:23 SYSDIV 22 USESYS 21:14 reserved 13 PWRDN 12 OEN 11 BYPASS 71 Type Reset Description R/W 0xF System Clock Divisor Specifies which divisor is used to generate the system clock from the PLL output (200 ...
Page 72
... Reserved bits return an indeterminate value, and should never be changed. Crystal Frequency (MHz) reserved 3.579545 MHz 3.6864 MHz 4 MHz 4.096 MHz 4.9152 MHz 5 MHz Preliminary LM3S101 Data Sheet Input Source Main oscillator Boot oscillator Boot oscillator / 4 (this is necessary if used as input to PLL) reserved 72 ...
Page 73
System Control Table 6-3. Default Crystal Field Values and PLL Programming Crystal Number (XTAL Binary Value) 1010 1011 1100 1101 1110 1111 Table 6-4. PLL Mode Control PWRDN Crystal Frequency (MHz) 5.12 MHz 6 MHz (reset value) ...
Page 74
... RO - This field specifies the value supplied to the PLL’s OD input This field specifies the value supplied to the PLL’s F input This field specifies the value supplied to the PLL’s R input. Preliminary LM3S101 Data Sheet ...
Page 75
System Control Register 19: Run-Mode Clock Gating Control 0 (RCGC0), offset 0x100 Register 20: Sleep-Mode Clock Gating Control 0 (SCGC0), offset 0x110 Register 21: Deep-Sleep-Mode Clock Gating Control 0 (DCGC0), offset 0x120 These registers control the clock gating logic. Each ...
Page 76
... March 22, 2006 COMP1 COMP0 RO RO R/W R reserved Preliminary LM3S101 Data Sheet reserved GPTM1 GPTM0 R SSI reserved RO R ...
Page 77
System Control Register 25: Run-Mode Clock Gating Control 2 (RCGC2), offset 0x108 Register 26: Sleep-Mode Clock Gating Control 2 (SCGC2), offset 0x118 Register 27: Deep-Sleep-Mode Clock Gating Control 2 (DCGC2), offset 0x128 These registers control the clock gating logic. Each ...
Page 78
... Reset Description RO 0 Reserved bits return an indeterminate value, and should never be changed. 0 Clear clock verification faults. Preliminary LM3S101 Data Sheet ...
Page 79
System Control Register 29: Allow Unregulated LDO to Reset the Part (LDOARST), offset 0x160 This register is provided as a means of allowing the LDO to reset the part if the voltage goes unregulated. Use this register to choose whether ...
Page 80
... Internal Memory The LM3S101 comes with bit-banded SRAM and flash memory. The flash controller provides a user-friendly interface, making flash programming a simple task. Flash protection can be applied to the flash memory on a 2-KB block basis. 7.1 Block Diagram Figure 7-1. Flash Block Diagram Cortex-M3 ...
Page 81
Internal Memory For example, if bit 3 at address 0x20001000 modified, the bit-band alias is calculated as: 0x22000000 + (0x1000 * 32 0x2202000C With the alias address calculated, an instruction performing a ...
Page 82
... March 22, 2006 Protection Read-only protection. The block may be read or executed but may not be written or erased. This mode is used to lock the block from further modification while allowing any read or execute access. No protection. The block may be written, erased, executed or read. Preliminary LM3S101 Data Sheet 82 ...
Page 83
Internal Memory The flash is programmed using the following sequence: 1. Write source data to the FMD register. 2. Write the target address to the FMA register. 3. Write the flash write key and the WRITE bit (a value of ...
Page 84
... Reset Description RO 0 Reserved bits return an indeterminate value, and should never be changed. R/W0 0x0F Enable 2-KB flash blocks to be written or erased (FMPPE register), or executed or read (FMPRE register). The policies may be combined as shown in Table 7-1 on page 81. Preliminary LM3S101 Data Sheet ...
Page 85
Internal Memory Register 3: U Second Reload (USECRL), offset 0x140 Note: Offset is relative to System Control base address of 0x400FE000 This register is provided as a means of creating a 1 usec tick divider reload value for the flash ...
Page 86
... R/W R/W R/W R/W R/W R Reset Description RO 0 Reserved bits return an indeterminate value, and should never be changed. 0 Address offset in flash where operation is performed. Preliminary LM3S101 Data Sheet OFFSET R/W R/W R/W R/W R ...
Page 87
Internal Memory Register 5: Flash Memory Data (FMD), offset 0x004 This register contains the data to be written during the programming cycle or read during the read cycle. Note that the contents of this register are undefined for a read ...
Page 88
... A write of 0 has no effect on the state of this bit. If read, the state of the previous mass erase access is provided. If the previous mass erase access is complete returned; otherwise, if the previous mass erase access is not complete returned. This can take up to 250 ms. Preliminary LM3S101 Data Sheet ...
Page 89
Internal Memory Bit/Field Name Type 1 ERASE R/W 0 WRITE R/W 89 Reset Description 0 Erase a page of flash memory If this bit is set, the page of flash main memory as specified by the contents of FMA is ...
Page 90
... Flash Memory Protection Read Enable (FMPRE) and Flash Memory Protection Program Enable (FMPPE) register (see page 84). Otherwise, no access has tried to improperly access the flash. Preliminary LM3S101 Data Sheet ...
Page 91
Internal Memory Register 8: Flash Controller Interrupt Mask (FCIM), offset 0x010 This register controls whether the flash controller generates interrupts to the controller. Flash Controller Interrupt Mask (FCIM) Offset 0x010 Type Reset ...
Page 92
... This bit indicates whether an interrupt was signaled because an improper access was attempted and was not masked. This bit is cleared by writing a 1. The ARIS bit in the FCRIS register is also cleared when the AMISC bit is cleared. Preliminary LM3S101 Data Sheet ...
Page 93
General-Purpose Input/Outputs (GPIOs) 8 General-Purpose Input/Outputs (GPIOs) The GPIO module is composed of three physical GPIO blocks, each corresponding to an individual GPIO port (Port A, Port B, and Port C). The GPIO module is FiRM-compliant and supports 2 to ...
Page 94
... JTAG functionality (GPIOAFSEL=1). Asserting a Power-On-Reset (POR external reset (RST) puts both groups of pins back to their default state. Each GPIO port is a separate hardware instantiation of the same physical block (see Figure 8-2). The LM3S101 microcontroller contains three of these physical GPIO blocks. March 22, 2006 PA0 ...
Page 95
General-Purpose Input/Outputs (GPIOs) Figure 8-2. GPIO Port Block Diagram Function Selection GPIOAFSEL Alternate Input Alternate Output Alternate Output Enable GPIO Input I/O Data GPIO Output GPIODATA GPIO Output Enable GPIODIR Interrupt Control GPIOIS GPIOIBE Interrupt GPIOIEV GPIOIM GPIORIS GPIOMIS GPIOICR ...
Page 96
... GPIO mode, where the GPIODATA register is used to read/write the corresponding pins. March 22, 2006 ADDR[9: 0x0C4 GPIODATA Returned Value Preliminary LM3S101 Data Sheet ...
Page 97
General-Purpose Input/Outputs (GPIOs) 8.2.5 Pad Configuration The pad configuration registers allow for GPIO pad configuration by software based on the application requirements. The pad configuration registers include the GPIODR2R, GPIODR4R, GPIODR8R, GPIOODR, GPIOPUR, GPIOPDR, GPIOSLR, and GPIODEN registers. 8.2.6 Identification ...
Page 98
... Data R/W Data direction R/W Interrupt sense R/W Interrupt both edges R/W Interrupt event R/W Interrupt mask enable RO Raw interrupt status RO Masked interrupt status W1C Interrupt clear a R/W Alternate function select Preliminary LM3S101 Data Sheet a Pin 2 Bit Value ...
Page 99
General-Purpose Input/Outputs (GPIOs) Table 8-3. GPIO Register Map Offset Name 0x500 GPIODR2R 0x000000FF 0x504 GPIODR4R 0x00000000 0x508 GPIODR8R 0x00000000 0x50C GPIOODR 0x00000000 0x510 GPIOPUR 0x000000FF 0x514 GPIOPDR 0x00000000 0x518 GPIOSLR 0x00000000 0x51C GPIODEN 0x000000FF 0xFD0 GPIOPeriphID4 0x00000000 0xFD4 GPIOPeriphID5 0x00000000 ...
Page 100
... Writes to this register only affect bits that are not masked by ipaddr[9:2] Register Operation” on page 95 for examples of reads and writes. Preliminary LM3S101 Data Sheet ...
Page 101
General-Purpose Input/Outputs (GPIOs) Register 2: GPIO Direction (GPIODIR), offset 0x400 The GPIODIR register is the data direction register. Bits set the GPIODIR register configure the corresponding pin output, while bits set to 0 configure ...
Page 102
... RO RO R/W R Reset Description 0 Reserved bits return an indeterminate value, and should never be changed. 0x00 GPIO Interrupt Sense 0: Edge on corresponding pin is detected (edge-sensitive) 1: Level on corresponding pin is detected (level-sensitive) Preliminary LM3S101 Data Sheet ...
Page 103
General-Purpose Input/Outputs (GPIOs) Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 The GPIOIBE register is the interrupt both-edges register. When the corresponding bit in the GPIO Interrupt Sense (GPIOIS) register (see page 102) is set to detect edges, bits ...
Page 104
... Reset Description 0 Reserved bits return an indeterminate value, and should never be changed. 0x00 GPIO Interrupt Event 0: Falling edge or Low levels on corresponding pins trigger interrupts. 1: Rising edge or High levels on corresponding pins trigger interrupts. Preliminary LM3S101 Data Sheet ...
Page 105
General-Purpose Input/Outputs (GPIOs) Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 The GPIOIM register is the interrupt mask register. Bits set to High in GPIOIM allow the corresponding pins to trigger their individual interrupts and the combined GPIOINTR line. Clearing ...
Page 106
... Reserved bits return an indeterminate value, and should never be changed. 0x00 GPIO Interrupt Raw Status Reflect the status of interrupt trigger condition detection on pins (raw, prior to masking). 0: Corresponding pin interrupt requirements not met. 1: Corresponding pin interrupt has met requirements. Preliminary LM3S101 Data Sheet ...
Page 107
General-Purpose Input/Outputs (GPIOs) Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 The GPIOMIS register is the masked interrupt status register. Bits read High in GPIOMIS reflect the status of input lines triggering an interrupt. Bits read as Low indicate ...
Page 108
... W1C W1C Reset Description 0 Reserved bits return an indeterminate value, and should never be changed. 0x00 GPIO Interrupt Clear 0: Corresponding interrupt is unaffected. 1: Corresponding interrupt is cleared. Preliminary LM3S101 Data Sheet ...
Page 109
General-Purpose Input/Outputs (GPIOs) Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 The GPIOAFSEL register is the mode control select register. Writing any bit in this register selects the hardware control for the corresponding GPIO line. All ...
Page 110
... Reset Description 0 Reserved bits return an indeterminate value, and should never be changed. 0xFF Output Pad 2-mA Drive Enable A write either corresponding 2-mA enable bit. The change is effective on the second clock cycle after the write. Preliminary LM3S101 Data Sheet ...
Page 111
General-Purpose Input/Outputs (GPIOs) Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 The GPIODR4R register is the 4-mA drive control register. It allows for each GPIO signal in the port to be individually configured without affecting the other pads. When ...
Page 112
... Reset Description 0 Reserved bits return an indeterminate value, and should never be changed. 0x00 Output Pad 8-mA Drive Enable A write either corresponding 8-mA enable bit. The change is effective on the second clock cycle after the write. Preliminary LM3S101 Data Sheet ...
Page 113
General-Purpose Input/Outputs (GPIOs) Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C The GPIOODR register is the open drain control register. Setting a bit in this register enables the open drain configuration of the corresponding GPIO pad. When the open ...
Page 114
... Reset Description 0 Reserved bits return an indeterminate value, and should never be changed. 0xFF Pad Weak Pull-Up Enable GPIOPDR A write GPIOPUR [n] enables. The change is effective on the second clock cycle after the write. Preliminary LM3S101 Data Sheet ...
Page 115
General-Purpose Input/Outputs (GPIOs) Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 The GPIOPDR register is the pull-down control register. When a bit is set enables a weak pull-down resistor on the corresponding GPIO signal. Setting a bit ...
Page 116
... RO RO R/W R Reset Description 0 Reserved bits return an indeterminate value, and should never be changed. 0 Slew Rate Limit Enable (8-mA drive only) 0: Slew rate control disabled. 1: Slew rate control enabled. Preliminary LM3S101 Data Sheet ...
Page 117
General-Purpose Input/Outputs (GPIOs) Register 18: GPIO Digital Input Enable (GPIODEN), offset 0x51C The GPIODEN register is the digital input enable register. By default, all GPIO signals are configured as digital inputs at reset. The only time that a pin should ...
Page 118
... Reset Description RO 0 Reserved bits return an indeterminate value, and should never be changed. RO 0x00 GPIO Peripheral ID Register[7:0] Preliminary LM3S101 Data Sheet PID4 ...
Page 119
General-Purpose Input/Outputs (GPIOs) Register 20: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to ...
Page 120
... Reset Description RO 0 Reserved bits return an indeterminate value, and should never be changed. RO 0x00 GPIO Peripheral ID Register[23:16] Preliminary LM3S101 Data Sheet PID6 ...
Page 121
General-Purpose Input/Outputs (GPIOs) Register 22: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to ...
Page 122
... Reset Description 0 Reserved bits return an indeterminate value, and should never be changed. 0x61 GPIO Peripheral ID Register[7:0] Can be used by software to identify the presence of this peripheral. Preliminary LM3S101 Data Sheet ...
Page 123
General-Purpose Input/Outputs (GPIOs) Register 24: GPIO Peripheral Identification 1(GPIOPeriphID1), offset 0xFE4 The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify ...
Page 124
... Reset Description 0 Reserved bits return an indeterminate value, and should never be changed. 0x18 GPIO Peripheral ID Register[23:16] Can be used by software to identify the presence of this peripheral. Preliminary LM3S101 Data Sheet ...
Page 125
General-Purpose Input/Outputs (GPIOs) Register 26: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to ...
Page 126
... Reset Description 0 Reserved bits return an indeterminate value, and should never be changed. 0x0D GPIO PrimeCell ID Register[7:0] Provides software a standard cross-peripheral identification system. Preliminary LM3S101 Data Sheet ...
Page 127
General-Purpose Input/Outputs (GPIOs) Register 28: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard ...
Page 128
... Reset Description 0 Reserved bits return an indeterminate value, and should never be changed. 0x05 GPIO PrimeCell ID Register[23:16] Provides software a standard cross-peripheral identification system. Preliminary LM3S101 Data Sheet ...
Page 129
General-Purpose Input/Outputs (GPIOs) Register 30: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard ...
Page 130
... General-Purpose Timers Programmable timers can be used to count or time external events that drive the Timer input pins. The LM3S101 controller General-Purpose Timer Module (GPTM) contains two GPTM blocks (Timer0 and Timer1). Each GPTM block provides two 16-bit timer/counters (referred to as TimerA and TimerB) that can be configured to operate independently as timers or event counters, or configured to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC) ...
Page 131
General-Purpose Timers 9.1 Block Diagram Figure 9-1. GPTM Block Diagram Timer A Control GPTMTAMATCHR Interrupt/Config GPTMCFG Timer A Interrupt GPTMCTL GPTMIMR GPTMRIS Timer B GPTMMIS Interrupt Timer B Control GPTMICR GPTMTBMATCHR System Clock 9.2 Functional Description The main components of ...
Page 132
... When RTC mode is selected for the first time, the counter is loaded with a value of 0x00000001. All subsequent load values must be written to the GPTM TimerA Match (GPTMTAMATCHR) register (see page 152) by the controller. March 22, 2006 . Likewise, a read access to GPTMTAR returns the . Preliminary LM3S101 Data Sheet 132 ...
Page 133
General-Purpose Timers The 32KHZ pin is dedicated to the 32-bit RTC function, and the input clock is 32 KHz. When software writes the TAEN bit in GPTMCTL, the counter starts counting up from its preloaded value of 0x00000001. When the ...
Page 134
... Note that the last two edges are not counted since the timer automatically clears the TnEN bit after the current count matches the value in the GPTMnMR register. March 22, 2006 a #Clock (T ) Max Time c 3.9321 332.9229 334.2336 335.5443 Preliminary LM3S101 Data Sheet Units 134 ...
Page 135
General-Purpose Timers Figure 9-2. 16-Bit Input Edge Count Mode Example Count 0x000A 0x0009 0x0008 0x0007 0x0006 Input Signal 9.2.3.3 16-Bit Input Edge Time Mode In Edge Time mode, the timer is configured as a free running down-counter initialized to the ...
Page 136
... Figure 9-4 shows how to generate an output PWM with a 1-ms period and a 66% duty cycle assuming a 50 MHz input clock and TnPWML=0 (duty cycle would be 33% for the TnPWML=1 configuration). For this example, the start value is GPTMnIRL=0xC350 and the match value is GPTMnMR=0x411A. March 22, 2006 GPTMTnR=X GPTMTnR=Y Preliminary LM3S101 Data Sheet GPTMTnR=Z Time 136 ...
Page 137
General-Purpose Timers Figure 9-4. 16-Bit PWM Mode Example Count 0xC350 0x411A TnPWML = 0 Output Signal TnPWML = 1 9.3 Initialization and Configuration This section shows module initialization and configuration examples for each of the supported timer modes. 9.3.1 32-bit ...
Page 138
... Load the timer start value into the Timern Interval Load (GPTMTnILR) register. 6. Load the desired event count into the Timern Match (GPTMTnMATCHR) register interrupts are required, set the CnMIM bit in the GPTM Interrupt Mask (GPTMIMR) register. March 22, 2006 Preliminary LM3S101 Data Sheet 138 ...
Page 139
General-Purpose Timers 8. Set the TnEN bit in the GPTMCTL register to enable the timer and begin waiting for edge events. 9. Poll the CnMRIS bit or wait for the interrupt to be generated (if enabled). In both cases, the ...
Page 140
... R/W TimerA prescale reset value R/W TimerB prescale reset value R/W TimerA prescale match reset value R/W TimerB prescale match reset value RO TimerA reset value RO TimerB reset value Preliminary LM3S101 Data Sheet See page 141 142 143 144 146 147 148 149 150 151 152 ...
Page 141
General-Purpose Timers Register 1: GPTM Configuration (GPTMCFG), offset 0x000 This register configures the global operation of the GPTM module. The value written to this register determines whether the GPTM is in 32- or 16-bit mode. GPTM Configuration (GPTMCFG) Offset 0x000 ...
Page 142
... The Timer mode is based on the timer configuration defined by bits 2:0 in the GPTMCFG register (16-or 32-bit). In 16-bit timer configuration, these bits control the 16-bit timer modes for TimerA. In 32-bit timer configuration, this register controls the mode and the contents of GPTMTBMR are ignored. Preliminary LM3S101 Data Sheet ...
Page 143
General-Purpose Timers Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008 This register configures the GPTM based on the configuration selected in GPTMCFG. When in 16- bit PWM mode, the TBTMR field should be set to 0x3, and the TBCMR should ...
Page 144
... TimerB stalling is enabled. 0 GPTM TimerB Enable 0: TimerB is disabled. 1: TimerB is enabled and begins counting or the capture logic is enabled based on the GPTMCFG register. 0 Read GPTM TimerA PWM Output Level 0: Output is unaffected. 1: Output is inverted. Preliminary LM3S101 Data Sheet ...
Page 145
General-Purpose Timers Bit Name Type 5 TAOTE R/W 4 RTCEN R/W 3:2 TAEVENT R/W 1 TASTALL R/W 0 TAEN R/W 145 Reset Description 0 GPTM TimerA Output Trigger Enable 0: The output TimerA trigger is disabled. 1: The output TimerA ...
Page 146
... Interrupt is disabled. 1: Interrupt is enabled. 0 GPTM Capture1 Event Interrupt Mask 0: Interrupt is disabled. 1: Interrupt is enabled. 0 GPTM Capture1 Match Interrupt Mask 0: Interrupt is disabled. 1: Interrupt is enabled. 0 GPTM TimerA Time-Out Interrupt Mask 0: Interrupt is disabled. 1: Interrupt is enabled. Preliminary LM3S101 Data Sheet ...
Page 147
General-Purpose Timers Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C This register shows the state of the GPTM's internal interrupt signal. These bits are set whether or not the interrupt is masked in the GPTMIMR register. Each bit can ...
Page 148
... This is the Capture1 Event interrupt status after masking. 0 GPTM Capture1 Match Masked Interrupt This is the Capture1 Match interrupt status after masking. 0 GPTM TimerA Time-Out Masked Interrupt This is the TimerA time-out interrupt status after masking. Preliminary LM3S101 Data Sheet ...
Page 149
General-Purpose Timers Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 This register is used to clear the status bits in the GPTMRIS and GPTMMIS registers. Writing bit clears the corresponding bit in the GPTMRIS and GPTMMIS ...
Page 150
... In 16-bit mode, this field reads as 0 and does not have an effect mode) on the state of GPTMTBILR. 0xFFFF GPTM TimerA Interval Load Register Low For both 16- and 32-bit modes, writing this field loads the counter for TimerA. A read returns the current value of GPTMTAILR. Preliminary LM3S101 Data Sheet R/W R/W ...
Page 151
General-Purpose Timers Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C This register is used to load the starting count value into TimerB. When the GPTM is configured to a 32-bit mode, GPTMTBILR returns the current value of TimerB and ...
Page 152
... GPTMTAILR, determines the duty cycle of the output PWM signal. When configured for Edge Count mode, this value along with GPTMTAILR, determines how many edge events are counted. The total number of edge events counted is equal to the value in GPTMTAILR minus this value. Preliminary LM3S101 Data Sheet R/W ...
Page 153
General-Purpose Timers Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 This register is used in 32-bit Real-Time Clock mode and 16-bit PWM and Input Edge Count modes. GPTM TimerB Match (GPTMTBMATCHR) Offset 0x034 Type RO RO ...
Page 154
... Reserved bits return an indeterminate value, and should never be changed. 0 GPTM TimerA Prescale The register loads this value on a write. A read returns the current value of the register. Refer to Table 9-1 on page 133 for more details and an example. Preliminary LM3S101 Data Sheet ...
Page 155
General-Purpose Timers Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C This register allows software to extend the range of the 16-bit timers. GPTM TimerB Prescale (GPTMTBPR) Offset 0x03C Type Reset 0 0 ...
Page 156
... R/W R Reset Description 0 Reserved bits return an indeterminate value, and should never be changed. 0 GPTM TimerA Prescale Match This value is used alongside GPTMTAMATCHR to detect timer match events while using a prescaler. Preliminary LM3S101 Data Sheet ...
Page 157
General-Purpose Timers Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 This register effectively extends the range of GPTMTBMATCHR to 24 bits. GPTM TimerB Prescale Match (GPTMTBPMR) Offset 0x044 Type Reset 0 ...
Page 158
... GPTMCFG 16-bit mode, this is read as zero. 0x0000 (16-bit mode) 0xFFFF GPTM TimerA Register Low A read returns the current value of the TimerA Count Register, except in Input Edge Count mode, when it returns the timestamp from the last edge event. Preliminary LM3S101 Data Sheet ...
Page 159
General-Purpose Timers Register 18: GPTM TimerB (GPTMTBR), offset 0x04C This register shows the current value of the TimerB counter in all cases except for Input Edge Count mode. When in this mode, this register contains the time at which the ...
Page 160
... The watchdog timer is used to regain control when a system has failed due to a software error or to the failure of an external device to respond in the expected way. The LM3S101 controller Watchdog Timer module consists of a 32-bit down counter, a programmable load register, interrupt generation logic, and a locking register. ...
Page 161
Watchdog Timer 10.2 Functional Description The Watchdog Timer module consists of a 32-bit down counter, a programmable load register, interrupt generation logic, and a locking register. Once the Watchdog Timer has been configured, the Watchdog Timer Lock (WDTLOCK) register is ...
Page 162
... Peripheral identification 0 RO Peripheral identification 1 RO Peripheral identification 2 RO Peripheral identification 3 RO PrimeCell identification 0 RO PrimeCell identification 1 RO PrimeCell identification 2 RO PrimeCell identification 3 Preliminary LM3S101 Data Sheet See page 167 168 169 170 171 172 173 174 175 176 177 178 179 ...
Page 163
Watchdog Timer Register 1: Watchdog Load (WDTLOAD), offset 0x000 This register is the 32-bit interval value used by the 32-bit counter. When this register is written, the value is immediately loaded and the counter restarts counting down from the new ...
Page 164
... WDTValue Reset Description 0xFFFFFFFF Watchdog Value Current value of the 32-bit down counter. Preliminary LM3S101 Data Sheet ...
Page 165
Watchdog Timer Register 3: Watchdog Control (WDTCTL), offset 0x008 This register is the watchdog control register. The watchdog timer can be configured to generate a reset signal (upon second time-out interrupt on time-out. When the watchdog interrupt has ...
Page 166
... Bit/Field Name Type 31:0 WDTIntClr WO March 22, 2006 WdogIntClr WdogIntClr Reset Description - Watchdog Interrupt Clear Preliminary LM3S101 Data Sheet 166 ...
Page 167
Watchdog Timer Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 This register is the raw interrupt status register. Watchdog interrupt events can be monitored via this register if the controller interrupt is masked. Watchdog Raw Interrupt Status (WDTRIS) Offset ...
Page 168
... Reset Description 0 Reserved bits return an indeterminate value, and should never be changed. 0x0 Watchdog Masked Interrupt Status Gives the masked interrupt state (after masking) of the WDTINTR interrupt. Preliminary LM3S101 Data Sheet ...
Page 169
Watchdog Timer Register 7: Watchdog Lock (WDTLOCK), offset 0xC00 Writing 0x1ACCE551 to the WDTLOCK register enables write access to all other registers. Writing any other value to the WDTLOCK register re-enables the locked state for register writes to all the ...
Page 170
... Reset Description 0 Reserved bits return an indeterminate value, and should never be changed. 0x00 WDT Peripheral ID Register[7:0] Preliminary LM3S101 Data Sheet PID4 ...
Page 171
Watchdog Timer Register 9: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 5 (WDTPeriphID5) Offset 0xFD4 Type RO RO ...
Page 172
... Reset Description 0 Reserved bits return an indeterminate value, and should never be changed. 0x00 WDT Peripheral ID Register[23:16] Preliminary LM3S101 Data Sheet PID6 ...
Page 173
Watchdog Timer Register 11: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 7 (WDTPeriphID7) Offset 0xFDC Type RO RO ...
Page 174
... Reset Description 0 Reserved bits return an indeterminate value, and should never be changed. 0x05 Watchdog Peripheral ID Register[7:0] Preliminary LM3S101 Data Sheet PID0 ...
Page 175
Watchdog Timer Register 13: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 1 (WDTPeriphID1) Offset 0xFE4 Type RO RO ...
Page 176
... Reset Description 0 Reserved bits return an indeterminate value, and should never be changed. 0x18 Watchdog Peripheral ID Register[23:16] Preliminary LM3S101 Data Sheet PID2 ...
Page 177
Watchdog Timer Register 15: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 3 (WDTPeriphID3) Offset 0xFEC Type RO RO ...
Page 178
... Reset Description 0 Reserved bits return an indeterminate value, and should never be changed. 0x0D Watchdog PrimeCell ID Register[7:0] Preliminary LM3S101 Data Sheet CID0 ...
Page 179
Watchdog Timer Register 17: Watchdog PrimeCell Identification 1(WDTPCellID1), offset 0xFF4 The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Primecell Identification 1 (WDTPCellID1) Offset 0xFF4 Type ...
Page 180
... Reset Description 0 Reserved bits return an indeterminate value, and should never be changed. 0x05 Watchdog PrimeCell ID Register[23:16] Preliminary LM3S101 Data Sheet CID2 ...
Page 181
Watchdog Timer Register 19: Watchdog PrimeCell Identification 3 (WDTPCellID0), offset 0xFFC The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Primecell Identification 3 (WDTPCellID3) Offset 0xFFC Type RO RO ...
Page 182
... Universal Asynchronous Receiver/Transmitter (UART) The Universal Asynchronous Receiver/Transmitter (UART) provides fully programmable, 16C550- type serial interface characteristics. The LM3S101 controller is equipped with one UART module. The UART has the following features: Separate transmit and receive FIFOs Programmable FIFO length, including 1-byte deep operation providing conventional double- ...
Page 183
Universal Asynchronous Receiver/Transmitter (UART) 11.1 Block Diagram Figure 11-1. UART Block Diagram System Clock Interrupt Control Interrupt Prime Cell UARTPCellID0 UARTPCellID1 UARTPCellID2 UARTPCellID3 Peripheral ID UARTPeriphID0 UARTPeriphID1 UARTPeriphID2 Control / Status UARTPeriphID3 UARTRSR/ECR UART PeriphID4 UARTPeriphID5 UARTLCRH UARTPeriphID6 UARTPeriphID7 11.2 ...
Page 184
... For transmission, data is written into the transmit FIFO. If the UART is enabled, it causes a data frame to start transmitting with the parameters March 22, 2006 UnTX 1-2 stop bits LSB MSB 1 5-8 data bits 0 n Parity bit Start if enabled Preliminary LM3S101 Data Sheet 184 ...
Page 185
Universal Asynchronous Receiver/Transmitter (UART) indicated in the UARTLCRH register. Data continues to be transmitted until there is no data left in the transmit FIFO. The BUSY bit in the UART Flag (UARTFR) register (see page 193) is asserted as soon ...
Page 186
... Write the integer portion of the BRD to the UARTIBRD register. 3. Write the fractional portion of the BRD to the UARTFBRD register. 4. Write the desired serial parameters to the UARTLCRH register (in this case, a value of 0x00000060). 5. Enable the UART by setting the UARTEN bit in the UARTCTL register. March 22, 2006 Preliminary LM3S101 Data Sheet 186 ...
Page 187
Universal Asynchronous Receiver/Transmitter (UART) 11.4 Register Map Table 11-1 lists the UART registers. All addresses given are relative to the UART’s base address: UART0: 0x4000C000 Note: The UART must be disabled (see the UARTEN bit in the UARTCTL register on ...
Page 188
... Register Descriptions The remainder of this section lists and describes the UART registers, in numerical order by address offset. March 22, 2006 Preliminary LM3S101 Data Sheet 188 ...
Page 189
Universal Asynchronous Receiver/Transmitter (UART) Register 1: UART Data (UARTDR), offset 0x000 This register is the data register (the interface to the FIFOs). When FIFOs are enabled, data written to this location is pushed onto the transmit FIFO. If FIFOs are ...
Page 190
... When this bit is set indicates that the received character did not have a valid stop bit. (A valid stop bit is 1.) 0 When written, the data that transmitted via the UART. When read, the data that was received by the UART. Preliminary LM3S101 Data Sheet 190 ...
Page 191
Universal Asynchronous Receiver/Transmitter (UART) Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 The UARTRSR/UARTECR register is the receive status register/error clear register. In addition to the UARTDR register, receive status can also be read from the UARTRSR register. If ...
Page 192
... This register cannot be written. 0 Reserved bits return an indeterminate value, and should never be changed. The UARTECR register cannot be read write to this register of any data clears the framing, parity, break and overrun flags. The UARTECR register cannot be read. Preliminary LM3S101 Data Sheet 192 ...
Page 193
Universal Asynchronous Receiver/Transmitter (UART) Register 3: UART Flag (UARTFR), offset 0x018 The UARTFR register is the flag register. After reset, the TXFF, RXFF, and BUSY bits are 0, and TXFE and RXFE bits are 1. UART Flag (UARTFR) Offset 0x018 ...
Page 194
... This bit is set as soon as the transmit FIFO becomes non-empty (regardless of whether UART is enabled or not). 0 Reserved bits return an indeterminate value, and should never be changed. Preliminary LM3S101 Data Sheet 194 ...
Page 195
Universal Asynchronous Receiver/Transmitter (UART) Register 4: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 The UARTIBRD register is the integer part of the baud-rate divisor value. All the bits are cleared on reset. The minimum possible divide ratio is 1 (when ...
Page 196
... Reset Description 0 Reserved bits return an indeterminate value, and should never be changed. 0 Fractional Baud-Rate Divisor Preliminary LM3S101 Data Sheet DIVFRAC R/W R/W R/W R/W R ...
Page 197
Universal Asynchronous Receiver/Transmitter (UART) Register 6: UART Line Control (UARTLCRH), offset 0x02C The UARTLCRH register is the line control register. Serial parameters such as data length, parity and stop bit selection are implemented in this register. When updating the baud-rate ...
Page 198
... If this bit is set Low level is continually output on the UnTX output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two frames (character periods). For normal use, this bit must be cleared to 0. Preliminary LM3S101 Data Sheet 198 ...
Page 199
Universal Asynchronous Receiver/Transmitter (UART) Register 7: UART Control (UARTCTL), offset 0x030 The UARTCTL register is the control register. All the bits are cleared on reset except for the Transmit Enable (TXE) and Receive Enable (RXE) bits, which are set to ...
Page 200
... UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows: 000: TX FIFO ≤ 1/8 full 001: TX FIFO ≤ 1/4 full 010: TX FIFO ≤ 1/2 full (default) 011: TX FIFO ≤ 3/4 full 100: TX FIFO ≤ 7/8 full 101-111: Reserved Preliminary LM3S101 Data Sheet ...