LM3S101-CRN20-XNPP ETC1 [List of Unclassifed Manufacturers], LM3S101-CRN20-XNPP Datasheet - Page 17
LM3S101-CRN20-XNPP
Manufacturer Part Number
LM3S101-CRN20-XNPP
Description
Microcontroller
Manufacturer
ETC1 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S101-CRN20-XNPP.pdf
(284 pages)
- Current page: 17 of 284
- Download datasheet (3Mb)
Architectural Overview
17
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ARM FiRM-compliant Watchdog Timer
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Synchronous Serial Interface (SSI)
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UART
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Analog Comparators
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16-bit Input Capture modes:
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16-bit PWM mode:
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32-bit down counter with a programmable load register
Separate watchdog clock with an enable
Programmable interrupt generation logic with interrupt masking
Lock register protection from runaway software
Reset generation logic with an enable/disable
ARM PrimeCell®-compliant peripheral and cell identification registers
User-enabled stalling when the controller asserts the CPU Halt flag during debug
Master or slave operation
Programmable clock bit rate and prescale
Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep
Programmable interface operation for Freescale SPI, National Semiconductor
MICROWIRE™, or Texas Instruments synchronous serial interfaces
Programmable data frame size from 4 to 16 bits
Internal loopback test mode for diagnostic/debug testing
Fully programmable 16C550-type UART
Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs to reduce CPU interrupt
service loading
Programmable baud-rate generator with fractional divider
Programmable FIFO length, including 1-byte deep operation providing conventional
double-buffered interface
FIFO trigger levels of 1/8, 1/4, 1/2, 3/4 and 7/8
Standard asynchronous communication bits for start, stop and parity
False start bit detection
Line-break generation and detection
Two independent integrated analog comparators
General-purpose timer function with an 8-bit prescaler
Programmable one-shot timer
Programmable periodic timer
User-enabled stalling when the controller asserts CPU Halt flag during debug
Input edge count capture
Input edge time capture
Simple PWM mode with software-programmable output inversion of the PWM signal
Preliminary
March 22, 2006
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