LM3S101-CRN20-XNPP ETC1 [List of Unclassifed Manufacturers], LM3S101-CRN20-XNPP Datasheet - Page 64

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LM3S101-CRN20-XNPP

Manufacturer Part Number
LM3S101-CRN20-XNPP
Description
Microcontroller
Manufacturer
ETC1 [List of Unclassifed Manufacturers]
Datasheet
March 22, 2006
Reset
Reset
Type
Type
Bit/Field
31:3
Software Reset Control (SRCR2)
Offset 0x048
2
1
0
RO
RO
31
15
0
0
Register 12: Software Reset Control 2 (SRCR2), offset 0x048
Writes to this register are masked by the bits in the Device Capabilities 4 (DC4) register (see
page 59).
RO
RO
30
14
0
0
reserved
PORTC
PORTB
PORTA
Name
RO
RO
29
13
0
0
RO
RO
28
12
0
0
Type
R/W
R/W
R/W
RO
RO
RO
27
11
0
0
RO
RO
26
10
0
0
reserved
Reset
RO
RO
25
0
9
0
0
0
0
0
Preliminary
RO
RO
24
0
8
0
Description
Reserved bits return an indeterminate value, and should
never be changed.
Reset control for GPIO Port C.
Reset control for GPIO Port B.
Reset control for GPIO Port A.
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
RO
RO
19
0
3
0
LM3S101 Data Sheet
PORTC PORTB PORTA
R/W
RO
18
0
2
0
R/W
RO
17
0
1
0
R/W
RO
16
0
0
0
64

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