LM3S101-CRN20-XNPP ETC1 [List of Unclassifed Manufacturers], LM3S101-CRN20-XNPP Datasheet - Page 41
![no-image](/images/no-image-200.jpg)
LM3S101-CRN20-XNPP
Manufacturer Part Number
LM3S101-CRN20-XNPP
Description
Microcontroller
Manufacturer
ETC1 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S101-CRN20-XNPP.pdf
(284 pages)
- Current page: 41 of 284
- Download datasheet (3Mb)
JTAG Interface
5.3.1.3
5.3.1.4
5.3.1.5
5.3.1.6
5.3.1.7
5.3.1.8
41
SAMPLE/PRELOAD Instruction
The SAMPLE/PRELOAD instruction connects the Boundary Scan data register chain between
TDI and TDO. This instruction samples the current state of the pad pins for observation and
preloads new test data. Each GPIO pad has an associated input, output, and output enable signal.
When the TAP controller enters the Capture DR state during this instruction, the input, output, and
output-enable signals to each of the GPIO pads is captured. These samples are serially shifted out
of TDO while the TAP controller is in the Shift DR state and can be used for observation or
comparison in various tests.
While these samples of the inputs, outputs, and output enables are being shifted out of the
Boundary Scan data register, new data is being shifted into the Boundary Scan data register from
TDI. Once the new data has been shifted into the Boundary Scan data register, the data is saved
in the parallel load registers when the TAP controller enters the Update DR state. This update of
the parallel load register preloads data into the Boundary Scan data register that is associated with
each input, output, and output enable. This preloaded data can be used with the EXTEST and
INTEST instructions to drive data into or out of the controller. Please see “Boundary Scan Data
Register” on page 42 for more information.
ABORT Instruction
The ABORT instruction connects the associated ABORT data register chain between TDI and
TDO. This instruction provides read and write access to the ABORT register of the ARM Debug
Access Port (DAP). Shifting the proper data into this data register clears various error bits or
initiates a DAP abort of a previous request. Please see the “ABORT Data Register” on page 43 for
more information.
DPACC Instruction
The DPACC instruction connects the associated DPACC data register chain between TDI and
TDO. This instruction provides read and write access to the DPACC register of the ARM Debug
Access Port (DAP). Shifting the proper data into this register and reading the data output from this
register allows read and write access to the ARM debug and status registers. Please see “DPACC
Data Register” on page 43 for more information.
APACC Instruction
The APACC instruction connects the associated APACC data register chain between TDI and
TDO. This instruction provides read and write access to the APACC register of the ARM Debug
Access Port (DAP). Shifting the proper data into this register and reading the data output from this
register allows read and write access to internal components and buses through the Debug Port.
Please see “APACC Data Register” on page 43 for more information.
IDCODE Instruction
The IDCODE instruction connects the associated IDCODE data register chain between TDI and
TDO. This instruction provides information on the manufacturer, part number, and version of the
controller. This information can be used by testing equipment and debuggers to automatically
configure their input and output data streams. IDCODE is the default instruction that is loaded into
the JTAG Instruction Register when a power-on-reset (POR) is asserted, TRST is asserted, or the
Test-Logic-Reset state is entered. Please see “IDCODE Data Register” on page 42 for more
information.
BYPASS Instruction
The BYPASS instruction connects the associated BYPASS data register chain between TDI and
TDO. This instruction is used to create a minimum length serial path between the TDI and TDO
ports. The BYPASS data register is a single-bit shift register. This instruction improves test
Preliminary
March 22, 2006
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