LM3S101-CRN20-XNPP ETC1 [List of Unclassifed Manufacturers], LM3S101-CRN20-XNPP Datasheet - Page 9

• Manufacturer Part Number: LM3S101-CRN20-XNPP
• Description: Microcontroller
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
General-Purpose Timers .............................................................................................................. 130
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Watchdog Timer............................................................................................................................ 160
Register 1:
Register 2:
Register 3:
9
GPIO Interrupt Mask (GPIOIM), offset 0x410 ....................................................................... 105
GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................... 106
GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ..................................................... 107
GPIO Interrupt Clear (GPIOICR), offset 0x41C .................................................................... 108
GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 .............................................. 109
GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................... 110
GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................... 111
GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................... 112
GPIO Open Drain Select (GPIOODR), offset 0x50C ............................................................ 113
GPIO Pull-Up Select (GPIOPUR), offset 0x510.................................................................... 114
GPIO Pull-Down Select (GPIOPDR), offset 0x514 ............................................................... 115
GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................... 116
GPIO Digital Input Enable (GPIODEN), offset 0x51C........................................................... 117
GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0......................................... 118
GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4......................................... 119
GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8......................................... 120
GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ........................................ 121
GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0......................................... 122
GPIO Peripheral Identification 1(GPIOPeriphID1), offset 0xFE4.......................................... 123
GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8......................................... 124
GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ........................................ 125
GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0............................................ 126
GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4............................................ 127
GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8............................................ 128
GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ........................................... 129
GPTM Configuration (GPTMCFG), offset 0x000 .................................................................. 141
GPTM TimerA Mode (GPTMTAMR), offset 0x004 ............................................................... 142
GPTM TimerB Mode (GPTMTBMR), offset 0x008 ............................................................... 143
GPTM Control (GPTMCTL), offset 0x00C ............................................................................ 144
GPTM Interrupt Mask (GPTMIMR), offset 0x018.................................................................. 146
GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C........................................................ 147
GPTM Masked Interrupt Status (GPTMMIS), offset 0x020................................................... 148
GPTM Interrupt Clear (GPTMICR), offset 0x024 .................................................................. 149
GPTM TimerA Interval Load (GPTMTAILR), offset 0x028.................................................... 150
GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................... 151
GPTM TimerA Match (GPTMTAMATCHR), offset 0x030..................................................... 152
GPTM TimerB Match (GPTMTBMATCHR), offset 0x034..................................................... 153
GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................... 154
GPTM TimerB Prescale (GPTMTBPR), offset 0x03C .......................................................... 155
GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ............................................. 156
GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ............................................. 157
GPTM TimerA (GPTMTAR), offset 0x048 ............................................................................ 158
GPTM TimerB (GPTMTBR), offset 0x04C............................................................................ 159
Watchdog Load (WDTLOAD), offset 0x000.......................................................................... 163
Watchdog Value (WDTVALUE), offset 0x004....................................................................... 164
Watchdog Control (WDTCTL), offset 0x008 ......................................................................... 165
Preliminary
March 22, 2006