LM3S101-CRN20-XNPP ETC1 [List of Unclassifed Manufacturers], LM3S101-CRN20-XNPP Datasheet - Page 137

• Manufacturer Part Number: LM3S101-CRN20-XNPP
• Description: Microcontroller
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

General-Purpose Timers
9.3
9.3.1
137
Figure 9-4.
Output
Signal
Initialization and Configuration
This section shows module initialization and configuration examples for each of the supported
timer modes.
32-bit One-Shot/Periodic Timer Mode
The GPTM is configured for 32-bit One-Shot and Periodic modes by the following sequence:
1.
2.
3.
4.
5.
6.
7.
In One-Shot mode, the timer stops counting after step 7. To re-enable the timer, repeat the
sequence. A timer configured in Periodic mode does not stop counting after it times out.
Ensure the timer is disabled (the TAEN bit in the GPTMCTL register is cleared) before making
any changes.
Write the Configuration Register (GPTMCFG) to a value of 0x0.
Set the TAMR field in the TimerA Mode Register (GPTMTAMR):
a.
b.
Load the start value into the TimerA Interval Load Register (GPTMTAILR).
If interrupts are required, set the TATOIM bit in the Interrupt Mask Register (GPTMIMR).
Set the TAEN bit in the GPTMCTL register to enable the timer and start counting.
Poll the TATORIS bit in the GPTMRIS register or wait for the interrupt to be generated (if
enabled). In both cases, the status flags are cleared by writing a 1 to the TATOCINT bit of the
Interrupt Clear Register (GPTMICR).
Write a value of 0x1 for One-Shot mode.
Write a value of 0x2 for Periodic mode.
TnPWML = 0
TnPWML = 1
0xC350
0x411A
16-Bit PWM Mode Example
Count
TnEN set
GPTMTnR=GPTMnMR
Preliminary
GPTMTnR=GPTMnMR
March 22, 2006
Time