LM3S101-CRN20-XNPP ETC1 [List of Unclassifed Manufacturers], LM3S101-CRN20-XNPP Datasheet - Page 80
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LM3S101-CRN20-XNPP
Manufacturer Part Number
LM3S101-CRN20-XNPP
Description
Microcontroller
Manufacturer
ETC1 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S101-CRN20-XNPP.pdf
(284 pages)
- Current page: 80 of 284
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7
7.1
7.2
7.2.1
March 22, 2006
Internal Memory
The LM3S101 comes with 2 KB of bit-banded SRAM and 8 KB of flash memory. The flash
controller provides a user-friendly interface, making flash programming a simple task. Flash
protection can be applied to the flash memory on a 2-KB block basis.
Block Diagram
Figure 7-1.
Functional Description
This section describes the functionality of both memories.
SRAM Memory
The internal SRAM of the Stellaris devices is located at address 0x20000000 of the device
memory map. To reduce the number of time consuming read-modify-write (RMW) operations,
ARM has introduced bit-banding technology in the new Cortex-M3 processor. With a bit-band-
enabled processor, certain regions in the memory map (SRAM and peripheral space) can use
address aliases to access individual bits in a single, atomic operation.
The bit-band alias is calculated by using the formula:
bit-band alias = bit-band base + (byte offset * 32) + (bit number * 4)
SRAM Array
Cortex-M3
Bridge
System Bus
Flash Block Diagram
DCode
ICode
APB
Preliminary
Flash Protection
Flash Control
Flash Timing
USECRL
FCMISC
FMPRE
FMPPE
FCRIS
FCIM
FMA
FMD
FMC
LM3S101 Data Sheet
Flash Array
80
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