LM3S101-CRN20-XNPP ETC1 [List of Unclassifed Manufacturers], LM3S101-CRN20-XNPP Datasheet - Page 57

• Manufacturer Part Number: LM3S101-CRN20-XNPP
• Description: Microcontroller
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

System Control
57
Reset
Reset
Type
Type
Bit/Field
31:26
23:18
15:5
Device Capabilities 2 (DC2)
Offset 0x014
3:1
25
24
17
16
4
0
RO
RO
31
15
0
0
Register 5: Device Capabilities 2 (DC2), offset 0x014
This register is predefined by the part and can be used to verify features. It also acts as a mask for
write operations to the Run-Mode Clock Gating Control 1 (RCGC1) register (see page 76),
Sleep-Mode Clock Gating Control 1 (SCGC1) register (see page 76), and Deep-Sleep-Mode
Clock Gating Control 1 (DCGC1) register (see page 76).
RO
RO
30
14
0
0
reserved
reserved
reserved
reserved
COMP1
COMP0
GPTM1
GPTM0
UART0
Name
SSI
RO
RO
29
13
0
0
reserved
RO
RO
28
12
0
0
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
27
11
0
0
reserved
RO
RO
26
10
0
0
COMP1 COMP0
Reset
RO
RO
25
1
9
0
0
1
1
0
1
1
0
1
0
1
Preliminary
RO
RO
24
1
8
0
Description
Reserved bits return an indeterminate value, and should
never be changed.
A 1 in this field indicates the presence of analog
comparator 1.
A 1 in this field indicates the presence of analog
comparator 0.
Reserved bits return an indeterminate value, and should
never be changed.
A 1 in this field indicates the presence of General-Purpose
Timer module 1.
A 1 in this field indicates the presence of General-Purpose
Timer module 0.
Reserved bits return an indeterminate value, and should
never be changed.
A 1 in this field indicates the presence of the SSI module.
Reserved bits return an indeterminate value, and should
never be changed.
A 1 in this field indicates the presence of the UART0
module.
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
reserved
SSI
RO
RO
20
0
4
1
RO
RO
19
0
3
0
reserved
RO
RO
18
0
2
0
March 22, 2006
GPTM1 GPTM0
RO
RO
17
1
1
0
UART0
RO
RO
16
1
0
1