LM3S101-CRN20-XNPP ETC1 [List of Unclassifed Manufacturers], LM3S101-CRN20-XNPP Datasheet - Page 38
LM3S101-CRN20-XNPP
Manufacturer Part Number
LM3S101-CRN20-XNPP
Description
Microcontroller
Manufacturer
ETC1 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S101-CRN20-XNPP.pdf
(284 pages)
- Current page: 38 of 284
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Figure 5-2.
5.2.3
5.2.4
March 22, 2006
Shift Registers
The shift registers consist of a serial shift register chain and a parallel load register. The serial shift
register chain samples specific information during the TAP controller’s CAPTURE states and
allows this information to be shifted out of TDO during the TAP controller’s SHIFT states. While the
sampled data is being shifted out of the chain on TDO, new data is being shifted into the serial shift
register on TDI. This new data is stored in the parallel load register during the TAP controller’s
UPDATE states. Each of the shift registers is discussed in detail in “Shift Registers” on page 38.
Operational Considerations
There are certain operational considerations when using the JTAG module. Because the JTAG
pins can be programmed to be GPIOs, board configuration and reset conditions on these pins
must be considered. In addition, because the JTAG module has integrated ARM Serial Wire
Debug, the method for switching between these two operational modes requires clarification.
1
0
Test Access Port State Machine
Run Test Idle
Test Logic
0
1
1
0
Preliminary
Select DR Scan
Capture DR
Update DR
Pause DR
Exit 1 DR
Exit 2 DR
Shift DR
1
0
0
1
0
1
1
0
1
0
1
0
1
0
Select IR Scan
Capture IR
Update IR
Pause IR
Exit 1 IR
Exit 2 IR
Shift IR
LM3S101 Data Sheet
1
0
0
1
0
1
1
0
1
0
1
0
38
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