LM3S101-CRN20-XNPP ETC1 [List of Unclassifed Manufacturers], LM3S101-CRN20-XNPP Datasheet - Page 217
LM3S101-CRN20-XNPP
Manufacturer Part Number
LM3S101-CRN20-XNPP
Description
Microcontroller
Manufacturer
ETC1 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S101-CRN20-XNPP.pdf
(284 pages)
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Universal Asynchronous Receiver/Transmitter (UART)
217
Reset
Reset
Type
Type
UART Primecell Identification 3 (UARTPCellID3)
Offset 0xFFC
RO
RO
31
15
0
0
31:8
7:0
Bit
Register 24: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the
reset values.
RO
RO
30
14
0
0
reserved
Name
CID3
RO
RO
29
13
0
0
RO
RO
28
12
0
0
reserved
Type
RO
RO
RO
RO
27
11
0
0
RO
RO
26
10
0
0
Reset
0xB1
0
RO
RO
25
0
9
0
Preliminary
Description
Reserved bits return an indeterminate value, and should never
be changed.
UART PrimeCell ID Register[31:24]
Provides software a standard cross-peripheral identification
system.
RO
RO
24
0
8
0
reserved
RO
RO
23
0
7
1
RO
RO
22
0
6
0
RO
RO
21
0
5
1
RO
RO
20
0
4
1
CID3
RO
RO
19
0
3
0
RO
RO
18
0
2
0
March 22, 2006
RO
RO
17
0
1
0
RO
RO
16
0
0
1
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