LM3S101-CRN20-XNPP ETC1 [List of Unclassifed Manufacturers], LM3S101-CRN20-XNPP Datasheet - Page 258
LM3S101-CRN20-XNPP
Manufacturer Part Number
LM3S101-CRN20-XNPP
Description
Microcontroller
Manufacturer
ETC1 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S101-CRN20-XNPP.pdf
(284 pages)
- Current page: 258 of 284
- Download datasheet (3Mb)
March 22, 2006
Reset
Reset
Type
Type
Bit/Field
Analog Comparator Reference Voltage Control (ACREFCTL)
Offset 0x010
31:10
RO
RO
31
15
0
0
7:4
3:0
9
8
Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x10
This register specifies whether the resistor ladder is powered on as well as the range and tap.
RO
RO
30
14
0
0
reserved
reserved
Name
VREF
RNG
EN
RO
RO
29
13
0
0
RO
RO
28
12
0
0
Type
R/W
R/W
R/W
RO
RO
RO
RO
27
11
0
0
RO
RO
26
10
0
0
Reset
0
0
0
0
0
EN
R/W
RO
RO
25
0
9
0
0
Preliminary
reserved
RNG
R/W
RO
RO
24
Description
Reserved bits return an indeterminate value, and should
never be changed.
The EN bit specifies whether the resistor ladder is powered
on. If 0, the resistor ladder is unpowered. If 1, the resistor
ladder is connected to the analog V
This bit is reset to 0 so that the internal reference consumes
the least amount of power if not used and programmed.
The RNG bit specifies the range of the resistor ladder. If 0, the
resistor ladder has a total resistance of 32 R. If 1, the resistor
ladder has a total resistance of 24 R.
Reserved bits return an indeterminate value, and should
never be changed.
The VREF bit field specifies the resistor ladder tap that is
passed through an analog multiplexer. The voltage
corresponding to the tap position is the internal reference
voltage available for comparison.
0
8
0
0
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
R/W
DD
RO
RO
19
0
3
0
0
.
LM3S101 Data Sheet
R/W
RO
RO
18
0
2
0
0
VREF
R/W
RO
RO
17
0
1
0
0
R/W
RO
RO
16
0
0
0
0
258
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