LM3S101-CRN20-XNPP ETC1 [List of Unclassifed Manufacturers], LM3S101-CRN20-XNPP Datasheet - Page 147
LM3S101-CRN20-XNPP
Manufacturer Part Number
LM3S101-CRN20-XNPP
Description
Microcontroller
Manufacturer
ETC1 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S101-CRN20-XNPP.pdf
(284 pages)
- Current page: 147 of 284
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General-Purpose Timers
147
Reset
Reset
Type
Type
Offset 0x01C
31:11
RO
RO
31
15
0
0
7:4
Bit
10
9
8
3
2
1
0
Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C
This register shows the state of the GPTM's internal interrupt signal. These bits are set whether or
not the interrupt is masked in the GPTMIMR register. Each bit can be cleared by writing a 1 to its
corresponding bit in GPTMICR.
RO
RO
30
14
0
0
TBTORIS
TATORIS
reserved
C2MRIS
reserved
C1MRIS
RTCRIS
C2ERIS
C1ERIS
Name
reserved
RO
RO
29
13
0
0
RO
RO
28
12
0
0
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
27
11
0
0
C2ERIS
RO
RO
26
10
0
0
Reset
0
0
0
0
0
0
0
0
0
C2MRIS TBTORIS
RO
RO
25
0
9
0
Preliminary
Description
Reserved bits return an indeterminate value, and should never
be changed.
GPTM Capture2 Event Raw Interrupt
This is the Capture2 Event interrupt status prior to masking.
GPTM Capture2 Match Raw Interrupt
This is the Capture2 Match interrupt status prior to masking.
GPTM TimerB Time-Out Raw Interrupt
This is the TimerB time-out interrupt status prior to masking.
Read as 0.
GPTM RTC Raw Interrupt
This is the RTC Event interrupt status prior to masking.
GPTM Capture1 Event Raw Interrupt
This is the Capture1 Event interrupt status prior to masking.
GPTM Capture1 Match Raw Interrupt
This is the Capture1 Match interrupt status prior to masking.
GPTM TimerA Time-Out Raw Interrupt
This the TimerA time-out interrupt status prior to masking.
RO
RO
24
0
8
0
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
reserved
RO
RO
21
0
5
0
RO
RO
20
0
4
0
RTCRIS C1ERIS
RO
RO
19
0
3
0
RO
RO
18
0
2
0
March 22, 2006
C1MRIS TATORIS
RO
RO
17
0
1
0
RO
RO
16
0
0
0
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