LM3S101-CRN20-XNPP ETC1 [List of Unclassifed Manufacturers], LM3S101-CRN20-XNPP Datasheet - Page 45

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LM3S101-CRN20-XNPP

Manufacturer Part Number
LM3S101-CRN20-XNPP
Description
Microcontroller
Manufacturer
ETC1 [List of Unclassifed Manufacturers]
Datasheet
System Control
6.1.2.3
6.1.2.4
45
3.
The external reset timing is shown in Figure 17-8 on page 280.
Power-On Reset (POR)
The Power-On Reset (POR) circuitry detects a rise in power-supply voltage and generates an on-
chip reset pulse. To use the on-chip circuitry, the RST input needs a pull-up resistor (1K to 10K
ohm).
The device must be operating within the specified operating parameters at the point when the on-
chip power-on reset pulse is complete. The specified operating parameters include supply voltage,
frequency, temperature, and so on. If the operating conditions are not met at the point of POR end,
the Stellaris controller does not operate correctly. In this case, the reset must be extended using
external circuitry. The RST input may be used with the circuit as shown in Figure 6-1.
Figure 6-1.
The R
the RST input. The diode discharges C
The Power-On Reset sequence is as follows:
1.
2.
3.
The internal POR is only active on the initial power-up of the controller. The Power-On Reset
timing is shown in Figure 17-9 on page 280.
Brown-Out Reset (BOR)
A drop in the input voltage resulting in the assertion of the internal brown-out detector can be used
to reset the controller. This is initially disabled and may be enabled by software.
The system provides a brown-out detection circuit that triggers if V
circuit is provided to guard against improper operation of logic and peripherals that operate off V
and not the LDO voltage. If a brown-out condition is detected, the system may generate a
controller interrupt or a system reset. The BOR circuit has a digital filter that protects against noise-
related detection. This feature may be optionally enabled.
The internal reset is released and the controller fetches and loads the initial stack pointer, the
initial program counter, and the first instruction designated by the program counter, and then
begins execution.
The controller waits for the later of external reset (RST) or internal POR to go inactive.
After the resets are inactive, the main crystal oscillator must be allowed to settle and there is
an internal main oscillator counter that takes from 15-30 ms to account for this. During this
time, internal reset to the rest of the controller is held active.
The internal reset is released and the controller fetches and loads the initial stack pointer, the
initial program counter, and the first instruction designated by the program counter, and then
begins execution.
1
and C
1
components define the power-on delay. The R
External Circuitry to Extend Reset
D
Preliminary
1
1
rapidly when the power supply is turned off.
R
C
1
1
R
2
RST
Stellaris
2
resistor mitigates any leakage from
DD
drops below V
March 22, 2006
BTH
. The
DD

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