LM3S101-CRN20-XNPP ETC1 [List of Unclassifed Manufacturers], LM3S101-CRN20-XNPP Datasheet - Page 75

• Manufacturer Part Number: LM3S101-CRN20-XNPP
• Description: Microcontroller
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

System Control
75
Reset
Reset
Type
Type
Run-Mode, Sleep-Mode and Deep-Sleep-Mode Clock Gating Control 0 (RCGC0, SCG0, and DCGC0)
Offset 0x100, 0x110, 0x120
RO
RO
31
15
0
0
Register 19: Run-Mode Clock Gating Control 0 (RCGC0), offset 0x100
Register 20: Sleep-Mode Clock Gating Control 0 (SCGC0), offset 0x110
Register 21: Deep-Sleep-Mode Clock Gating Control 0 (DCGC0), offset 0x120
These registers control the clock gating logic. Each bit controls a clock enable for a given
interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled (saving power). The reset state of these bits is 0 (unclocked) unless
otherwise noted, so that all functional units are disabled. It is the responsibility of software to
enable the ports necessary for the application. Note that these registers may contain more bits
than there are interfaces, functions, or units to control. This is to assure reasonable code
compatibility with other family and future parts.
RCGC0 is the clock configuration register for running operation, SCGC0 for Sleep operation, and
DCGC0 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration
(RCC) register (see page 70) specifies that the system uses sleep modes.
The bit diagram for these three registers is shown below. Bits have the same definitions as DC1
(see page 56) and use DC1 as the mask.
RO
RO
30
14
0
0
RO
RO
29
13
0
0
RO
RO
28
12
0
0
RO
RO
27
11
0
0
RO
RO
26
10
0
0
reserved
RO
RO
25
0
9
0
Preliminary
RO
RO
24
0
8
0
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
WDT
R/W
RO
19
0
3
0
SWO
R/W
RO
18
0
2
0
March 22, 2006
SWD
R/W
RO
17
0
1
0
JTAG
R/W
RO
16
0
0
1