LM3S101-CRN20-XNPP ETC1 [List of Unclassifed Manufacturers], LM3S101-CRN20-XNPP Datasheet - Page 195
![no-image](/images/no-image-200.jpg)
LM3S101-CRN20-XNPP
Manufacturer Part Number
LM3S101-CRN20-XNPP
Description
Microcontroller
Manufacturer
ETC1 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S101-CRN20-XNPP.pdf
(284 pages)
- Current page: 195 of 284
- Download datasheet (3Mb)
Universal Asynchronous Receiver/Transmitter (UART)
195
Reset
Reset
Type
Type
UART Integer Baud-Rate Divisor
Offset 0x024
31:16
R/W
RO
31
15
0
0
15:0
Bit
Register 4: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024
The UARTIBRD register is the integer part of the baud-rate divisor value. All the bits are cleared
on reset. The minimum possible divide ratio is 1 (when UARTIBRD=0), in which case the
UARTFBRD register is ignored. When changing the UARTIBRD register, the new value does not
take effect until transmission/reception of the current character is complete. Any changes to the
baud-rate divisor must be followed by a write to the UARTLCRH register. See “Baud-Rate
Generation” on page 184 for configuration details.
R/W
RO
30
14
0
0
reserved
DIVINT
Name
R/W
RO
29
13
0
0
R/W
RO
28
12
0
0
Type
R/W
RO
R/W
RO
27
11
0
0
R/W
RO
26
10
0
0
Reset
0x00
0
R/W
RO
25
0
9
0
Preliminary
Description
Reserved bits return an indeterminate value, and should never
be changed.
Integer Baud-Rate Divisor
R/W
RO
24
0
8
0
reserved
DIVINT
R/W
RO
23
0
7
0
R/W
RO
22
0
6
0
R/W
RO
21
0
5
0
R/W
RO
20
0
4
0
R/W
RO
19
0
3
0
R/W
RO
18
0
2
0
March 22, 2006
R/W
RO
17
0
1
0
R/W
RO
16
0
0
0
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