LM3S101-CRN20-XNPP ETC1 [List of Unclassifed Manufacturers], LM3S101-CRN20-XNPP Datasheet - Page 234
![no-image](/images/no-image-200.jpg)
LM3S101-CRN20-XNPP
Manufacturer Part Number
LM3S101-CRN20-XNPP
Description
Microcontroller
Manufacturer
ETC1 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S101-CRN20-XNPP.pdf
(284 pages)
- Current page: 234 of 284
- Download datasheet (3Mb)
March 22, 2006
Reset
Reset
Type
Type
SSI Clock Prescale (SSICPSR)
Offset 0x010
Bit/Field
RO
RO
31
15
0
0
31:8
7:0
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010
SSICPSR is the clock prescale register and specifies the division factor by which the system clock
must be internally divided before further use.
The value programmed into this register must be an even number between 2 and 254. The least-
significant bit of the programmed number is hard-coded to zero. If an odd number is written to this
register, data read back from this register has the least-significant bit as zero.
RO
RO
30
14
0
0
CPSDVSR
reserved
Name
RO
RO
29
13
0
0
reserved
RO
RO
28
12
0
0
Type
RO
RO
R/W
27
11
0
0
RO
RO
RO
26
10
0
0
Reset
RO
RO
25
0
0
0
9
0
Preliminary
RO
RO
24
0
8
0
Description
Reserved bits return an indeterminate value, and should
never be changed.
This value must be an even number from 2 to 254, depending
on the frequency of SSIClk. The LSB always returns 0 on
reads.
SSI Clock Prescale Divisor
reserved
R/W
RO
23
0
7
0
R/W
RO
22
0
6
0
R/W
RO
21
0
5
0
R/W
RO
20
0
4
0
CPSDVSR
R/W
RO
19
0
3
0
LM3S101 Data Sheet
R/W
RO
18
0
2
0
R/W
RO
17
0
1
0
R/W
RO
16
0
0
0
234
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