LM3S101-CRN20-XNPP ETC1 [List of Unclassifed Manufacturers], LM3S101-CRN20-XNPP Datasheet - Page 183

• Manufacturer Part Number: LM3S101-CRN20-XNPP
• Description: Microcontroller
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

Universal Asynchronous Receiver/Transmitter (UART)
11.1
Figure 11-1.
11.2
11.2.1
183
System Clock
Interrupt
UART PeriphID4
UARTPeriphID0
UARTPeriphID1
UARTPeriphID2
UARTPeriphID3
UARTPeriphID5
UARTPeriphID6
UARTPeriphID7
UARTPCellID0
UARTPCellID1
UARTPCellID2
UARTPCellID3
Peripheral ID
Prime Cell
Block Diagram
Functional Description
The Stellaris UART performs the functions of parallel-to-serial and serial-to-parallel conversions. It
is similar in functionality to a 16C550 UART, but is not register compatible.
The UART is configured for transmit and/or receive via the TXE and RXE bits of the UART Control
(UARTCTL) register (see page 199). Transmit and receive are both enabled out of reset. Before
any control registers are programmed, the UART must be disabled by clearing the UARTEN bit in
UARTCTL. If the UART is disabled during a TX or RX operation, the current transaction is
completed prior to the UART stopping.
Transmit/Receive Logic
The transmit logic performs parallel-to-serial conversion on the data read from the transmit FIFO.
The control logic outputs the serial bit stream beginning with a start bit, and followed by the data
bits (LSB first), parity bit, and the stop bits according to the programmed configuration in the
control registers. See Figure 11-2 for details.
UART Block Diagram
Interrupt Control
Control / Status
UARTRSR/ECR
UARTLCRH
UARTIFLS
UARTDR
UARTCTL
UARTMIS
UARTRIS
UARTICR
UARTFR
UARTIM
Preliminary
UARTFBRD
UARTIBRD
Baud Rate
Generator
TXFIFO
RXFIFO
16x8
16x8
.
.
.
.
.
.
Transmitter
Receiver
March 22, 2006
UnTx
UnRx