LM3S101-CRN20-XNPP ETC1 [List of Unclassifed Manufacturers], LM3S101-CRN20-XNPP Datasheet - Page 50
![no-image](/images/no-image-200.jpg)
LM3S101-CRN20-XNPP
Manufacturer Part Number
LM3S101-CRN20-XNPP
Description
Microcontroller
Manufacturer
ETC1 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S101-CRN20-XNPP.pdf
(284 pages)
- Current page: 50 of 284
- Download datasheet (3Mb)
Table 6-1.
March 22, 2006
Offset
0x018
0x01C
Local Control
0x030
0x034
0x040
0x044
0x048
0x050
0x054
0x058
0x05C
0x060
0x064
System Control
0x100
0x104
0x108
0x110
0x114
0x118
0x120
0x124
0x128
0x150
0x160
Name
DC3
DC4
PBORCTL
LDOPCTL
SRCR0
SRCR1
SRCR2
RIS
IMC
MISC
RESC
RCC
PLLCFG
RCGC0
RCGC1
RCGC2
SCGC0
SCGC1
SCGC2
DCGC0
DCGC1
DCGC2
CLKVCLR
LDOARST
System Control Register Map (Sheet 2 of 2)
Reset
0x00007FFD
0x810003C0
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000001
0x00000000
0x00000000
0x00000001
0x00000000
0x00000000
0x00000001
0x00000000
0x00000000
0x00000000
0x00000000
0x7803AC0
0x7
-
-
Type
R/W1C
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Preliminary
RO
RO
RO
RO
Description
Device Capabilities 3
Device Capabilities 4
Power-On and Brown-Out Reset Control
LDO Power Control
Software Reset Control 0
Software Reset Control 1
Software Reset Control 2
Raw Interrupt Status
Interrupt Mask Control
Masked Interrupt Status and Clear
Reset Cause
Run-Mode Clock Configuration
XTAL to PLL translation
Run-Mode Clock Gating Control 0
Run-Mode Clock Gating Control 1
Run-Mode Clock Gating Control 2
Sleep-Mode Clock Gating Control 0
Sleep-Mode Clock Gating Control 1
Sleep-Mode Clock Gating Control 2
Deep-Sleep-Mode Clock Gating Control 0
Deep-Sleep-Mode Clock Gating Control 1
Deep-Sleep-Mode Clock Gating Control 2
Clock verification clear
Allow unregulated LDO to reset the part
LM3S101 Data Sheet
See
page
60
61
62
63
64
65
66
68
69
70
74
75
76
77
75
76
77
75
76
77
78
79
58
59
50
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