LM3S101-CRN20-XNPP ETC1 [List of Unclassifed Manufacturers], LM3S101-CRN20-XNPP Datasheet - Page 58
LM3S101-CRN20-XNPP
Manufacturer Part Number
LM3S101-CRN20-XNPP
Description
Microcontroller
Manufacturer
ETC1 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S101-CRN20-XNPP.pdf
(284 pages)
- Current page: 58 of 284
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March 22, 2006
Reset
Reset
Type
Type
30:25
23:10
Bit/Field
Device Capabilities 3 (DC3)
Offset 0x018
5:0
31
24
32KHz
9
8
7
6
RO
RO
31
15
1
0
Register 6: Device Capabilities 3 (DC3), offset 0x018
This register is predefined by the part and can be used to verify features.
RO
RO
30
14
0
0
reserved
reserved
reserved
32KHz
Name
CCP0
C0o
C0+
C1-
C0-
RO
RO
29
13
0
0
reserved
RO
RO
28
12
0
0
reserved
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
27
11
0
0
RO
RO
26
10
0
0
Reset
C1-
RO
RO
25
0
9
1
1
0
1
0
1
1
1
1
0
Preliminary
CCP0
C0o
RO
RO
24
1
8
1
Description
A 1 in this field indicates the presence of a 32-KHz input
pin.
Reserved bits return an indeterminate value, and should
never be changed.
A 1 in this field indicates the presence of the Capture/
Compare/PWM pin 0.
Reserved bits return an indeterminate value, and should
never be changed.
A 1 in this field indicates the presence of the C1- pin.
A 1 in this field indicates the presence of the C0o pin.
A 1 in this field indicates the presence of the C0+ pin.
A 1 in this field indicates the presence of the C0- pin.
Reserved bits return an indeterminate value, and should
never be changed.
C0+
RO
RO
23
0
7
1
C0-
RO
RO
22
0
6
1
RO
RO
21
0
5
0
RO
RO
20
0
4
0
reserved
RO
RO
19
0
3
0
reserved
LM3S101 Data Sheet
RO
RO
18
0
2
0
RO
RO
17
0
1
0
RO
RO
16
0
0
0
58
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