LM3S101-CRN20-XNPP ETC1 [List of Unclassifed Manufacturers], LM3S101-CRN20-XNPP Datasheet - Page 192

• Manufacturer Part Number: LM3S101-CRN20-XNPP
• Description: Microcontroller
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

March 22, 2006
Write-Only Error Clear (UARTECR)
31:8
7:0
Bit
2
1
0
reserved
Name
DATA
BE
PE
FE
Type
WO
WO
RO
RO
RO
Reset
0
0
0
0
0
Preliminary
Description
UART Break Error
This bit is set to 1 when a break condition is detected, indicating
that the received data input was held Low for longer than a full-
word transmission time (defined as start, data, parity, and stop
bits).
This bit is cleared to 0 by a write to UARTECR.
In FIFO mode, this error is associated with the character at the
top of the FIFO. When a break occurs, only one 0 character is
loaded into the FIFO. The next character is only enabled after
the receive data input goes to a 1 (marking state) and the next
valid start bit is received.
This register cannot be written.
UART Parity Error
This bit is set to 1 when the parity of the received data character
does not match the parity defined by bits 2 and 7 of the
UARTLCRH register.
This bit is cleared to 0 by a write to UARTECR.
This register cannot be written.
UART Framing Error
This bit is set to 1 when the received character does not have a
valid stop bit (a valid stop bit is 1).
This bit is cleared to 0 by a write to UARTECR.
In FIFO mode, this error is associated with the character at the
top of the FIFO.
This register cannot be written.
Reserved bits return an indeterminate value, and should never
be changed. The UARTECR register cannot be read.
A write to this register of any data clears the framing, parity,
break and overrun flags. The UARTECR register cannot be
read.
LM3S101 Data Sheet
192