LM3S101-CRN20-XNPP ETC1 [List of Unclassifed Manufacturers], LM3S101-CRN20-XNPP Datasheet - Page 86

• Manufacturer Part Number: LM3S101-CRN20-XNPP
• Description: Microcontroller
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

March 22, 2006
Reset
Reset
Type
Type
Bit/Field
Flash Memory Address (FMA)
Offset 0x000
31:12
RO
RO
31
15
0
0
11:0
Register 4: Flash Memory Address (FMA), offset 0x000
During a write operation, this register contains a 4-byte-aligned address and specifies where the
data is written. During erase operations, this register contains a 1 KB-aligned address and
specifies which page is erased. Note that the alignment requirements must be met by software or
the results of the operation are unpredictable.
RO
RO
30
14
0
0
reserved
OFFSET
reserved
Name
RO
RO
29
13
0
0
RO
RO
28
12
0
0
Type
R/W
R/W
RO
RO
27
11
0
0
R/W
RO
26
10
0
0
Reset
0
0
R/W
RO
25
0
9
0
Preliminary
R/W
RO
24
Description
Reserved bits return an indeterminate value, and should
never be changed.
Address offset in flash where operation is performed.
0
8
0
reserved
R/W
RO
23
0
7
0
R/W
RO
22
0
6
0
OFFSET
R/W
RO
21
0
5
0
R/W
RO
20
0
4
0
R/W
RO
19
0
3
0
LM3S101 Data Sheet
R/W
RO
18
0
2
0
RO
R/W
17
0
1
0
RO
R/W
16
0
0
0
86