LM3S101-CRN20-XNPP ETC1 [List of Unclassifed Manufacturers], LM3S101-CRN20-XNPP Datasheet - Page 191

• Manufacturer Part Number: LM3S101-CRN20-XNPP
• Description: Microcontroller
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

Universal Asynchronous Receiver/Transmitter (UART)
191
Reset
Reset
Reset
Reset
Type
Type
Type
Type
Read-Only Receive Status (UARTRSR)
UART Receive Status (UARTRSR): Read
Offset 0x004
UART Error Clear (UARTECR): Write
Offset 0x004
RO
WO
WO
31
RO
15
31
15
0
0
0
0
31:4
Bit
3
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004
The UARTRSR/UARTECR register is the receive status register/error clear register.
In addition to the UARTDR register, receive status can also be read from the UARTRSR register. If
the status is read from this register, then the status information corresponds to the entry read from
UARTDR prior to reading UARTRSR. The status information for overrun is set immediately when
an overrun condition occurs.
A write of any value to the UARTECR register clears the framing, parity, break, and overrun errors.
All the bits are cleared to 0 on reset.
RO
WO
WO
30
RO
14
30
14
0
0
0
0
reserved
Name
OE
RO
WO
WO
29
RO
13
29
13
0
0
0
0
RO
WO
WO
28
RO
12
28
12
0
0
0
0
reserved
Type
RO
RO
RO
WO
WO
27
RO
11
27
11
0
0
0
0
RO
WO
WO
26
RO
10
26
10
0
0
0
0
reserved
Reset
0
0
RO
WO
WO
25
RO
25
0
9
0
0
9
0
Preliminary
Description
Reserved bits return an indeterminate value, and should never
be changed. The UARTRSR register cannot be written.
UART Overrun Error
When this bit is set to 1, data is received and the FIFO is already
full. This bit is cleared to 0 by a write to UARTECR.
The FIFO contents remain valid since no further data is written
when the FIFO is full, only the contents of the shift register are
overwritten. The CPU must now read the data in order to empty
the FIFO.
This register cannot be written.
RO
WO
WO
24
24
RO
0
8
0
0
8
0
reserved
reserved
RO
WO
WO
23
RO
23
0
7
0
0
7
0
RO
WO
WO
22
RO
22
0
6
0
0
6
0
RO
WO
WO
21
RO
21
0
5
0
0
5
0
RO
WO
WO
20
20
RO
0
4
0
0
4
0
DATA
OE
RO
WO
WO
19
RO
19
0
3
0
0
3
0
BE
RO
WO
WO
18
RO
18
0
2
0
0
2
0
March 22, 2006
PE
RO
WO
WO
17
RO
17
0
1
0
0
1
0
RO
WO
FE
WO
16
RO
16
0
0
0
0
0
0