PEF2256 INFINEON [Infineon Technologies AG], PEF2256 Datasheet - Page 458

• Manufacturer Part Number: PEF2256
• Description: E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

XFW2
XREP2
RLI2
CEC2
Receive Signaling Status Register 2 (Read)
Value after reset: 00
RSIS2
RSIS2 relates to the last received HDLC channel 2 frame; it is copied into RFIFO2 when
end-of-frame is recognized (last byte of each stored frame).
VFR2
User’s Manual
Hardware Description
VFR2
7
Transmit FIFO Write Enable - HDLC Channel 2
Data can be written to the XFIFO2.
Transmission Repeat - HDLC Channel 2
Status indication of CMDR2.XREP2.
Receive Line Inactive - HDLC Channel 2
Neither flags as interframe time fill nor frames are received via the
signaling time slot.
Command Executing - HDLC Channel 2
0
1
Note:CEC2 will be active up to 2.5 periods of the current system data
Valid Frame - HDLC Channel 2
Determines whether a valid frame has been received.
1
0
An invalid frame is either
– a frame which is not an integer number of 8 bits (n
– a frame which is too short taking into account the operation mode
RDO2
H
(e.g. 25 bits), or
selected via MODE2 (MDS2(2:0)) and the selection of receive CRC
ON/OFF (CCR3.RCRC2) as follows:
• MDS2(2:0) = 011 (16 bit Address),
RCRC2=0 : 4 bytes; RCRC2=1 : 3 or 4 bytes
No command is currently executed, the CMDR3 register can be
written to.
A command (written previously to CMDR3) is currently
executed, no further command can be temporarily written in
CMDR3 register.
rate.
Valid
Invalid
CRC162
RAB2
458
HA12
HA02
DS1.1, 2003-10-23
T1/J1 Registers
PEF 2256 H/E
LA2
8 bits) in length
0
FALC
(AA)
®
56