PEF2256 INFINEON [Infineon Technologies AG], PEF2256 Datasheet - Page 30

• Manufacturer Part Number: PEF2256
• Description: E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

Table 2
Pin or
Ball No.
3 (C2)
User’s Manual
Hardware Description
Name
RL1
RDIP
ROID
Pin Definitions - Line Interface
Pin
Type
I
I
I
Buffer
Type
analog Line Receiver Input 1
digital
digital
Function
Analog input from the external transformer.
Selected by LIM1.DRS = 0.
Receive Data Input Positive
Digital input for received dual-rail PCM(+)
route signal which is latched with the
internally recovered receive route clock. An
internal DPLL extracts the receive route clock
from the incoming data pulses. The duty cycle
of the received signal has to be close to 50%.
The dual-rail mode is selected if
LIM1.DRS = 1
Input polarity is selected by bit RC0.RDIS
(active low by default), line coding is selected
by FMR0.RC(1:0).
Receive Optical Interface Data
Unipolar data received from a fiber-optical
interface. Latching of data is done with the
falling edge of RCLKI. Input polarity is
selected by bit RC0.RDIS.
The single-rail mode is selected if
LIM1.DRS = 1
If CMI coding is selected
(FMR0.RC(1:0) = 01
recovers clock and data, no clock signal on
RCLKI is required.
30
B
B
and FMR0.RC1 = 1
and FMR0.RC1 = 0
B
), an internal DPLL
External Signals
DS1.1, 2003-10-23
PEF 2256 H/E
FALC
B
B
.
.
®
56