PEF2256 INFINEON [Infineon Technologies AG], PEF2256 Datasheet - Page 27

• Manufacturer Part Number: PEF2256
• Description: E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

Table 1
Pin or
Ball No.
51 (E9)
52 (E7)
53 (D7)
User’s Manual
Hardware Description
Name
RD
DS
RW
ALE
WR
Pin Definitions - Microprocessor Interface (cont’d)
Pin
Type
I
I
I
I
I
Buffer
Type
PU
PU
PU
PU
PU
Function
Address Latch Enable
This signal allows the FALC
connected to a multiplexed address/data bus
without the need for external latches. The
address information provided on lines A(7:0)
is internally latched with the falling edge of
ALE. In this application, pins A(7:0) must be
connected to the data bus pins externally.
In case of demultiplexed mode this pin can be
connected directly to
Read Enable
Used in Intel bus mode. This signal indicates
a read operation. When the FALC
selected via CS, the RD signal enables the
bus drivers to output data from an internal
register addressed by A(7:0) to the Data Bus.
Data Strobe
Used in Motorola bus mode. This pin serves
as input to control read/write operations.
Write Enable
Used in Intel bus mode. This signal indicates
a write operation. When CS is active the
FALC
provided on the data bus.
Read/Write Enable
Used in Motorola bus mode. This signal
distinguishes between read and write
operations.
27
®
56 loads an internal register with data
V
DD
or can be left open.
®
External Signals
DS1.1, 2003-10-23
56 to be
PEF 2256 H/E
®
FALC
56 is
®
56