PEF2256 INFINEON [Infineon Technologies AG], PEF2256 Datasheet - Page 118

• Manufacturer Part Number: PEF2256
• Description: E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

4.6.3
To perform an effective circuit test a payload loop is implemented. The payload
loop-back (FMR2.PLB) loops the data stream from the receiver section back to
transmitter section. The looped data passes the complete receiver including the wander
and jitter compensation in the receive elastic store and is output on pin RDO. Instead of
the data an AIS signal (FMR2.SAIS) can be sent to the system interface.
The framing bits, CRC4 and spare bits are not looped, if XSP.TT0 = 0. They are
generated by the FALC
on pins XL1/2 or XDOP/XDON are clocked with SCLKR instead of SCLKX. If
XSP.TT0 = 1 the received time slot 0 is sent back transparently to the line interface. Data
on the following pins is ignored: XDI, XSIG, SCLKX, SYPX and XMFS. All the received
data is processed normally.
Figure 41
User’s Manual
Hardware Description
RL1
RL2
XL1
XL2
Payload Loop-Back
Payload Loop (E1)
Clock +
Data
Recovery
®
56 transmitter. If the PLB is enabled the transmitter and the data
Trans.
Framer
RCLK
Rec.
Framer
118
Elast.
Store
Elast.
Store
Functional Description E1
AIS-GEN
MUX
DS1.1, 2003-10-23
PEF 2256 H/E
FALC
RDO
SCLKR
XDI
SCLKX
ITS09748
®
56