PEF2256 INFINEON [Infineon Technologies AG], PEF2256 Datasheet - Page 431

• Manufacturer Part Number: PEF2256
• Description: E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

XLS
XLO
User’s Manual
Hardware Description
PRBS Status
LCR1.EPRM = 1: The current status of the PRBS synchronizer is
indicated in this bit. It is set high if the synchronous state is reached
even in the presence of a bit error rate of up to 10
containing all zeros or all ones with/without framing bits is also a valid
pseudo-random binary sequence.
Transmit Line Short
Significant only if the ternary line interface is selected by
LIM1.DRS = 0.
0 =
1 =
Transmit Line Open
0 =
1 =
Normal operation. No short is detected.
Normal operation
The XL1 and XL2 are shortened for at least 3 pulses. As a
reaction of the short the pins XL1 and XL2 are automatically
forced into a high-impedance state if bit XPM2.DAXLT is reset.
After 128 consecutive pulse periods the outputs XL1/2 are
activated again and the internal transmit current limiter is
checked. If a short between XL1/2 is still further active the
outputs XL1/2 are in high-impedance state again. When the
short disappears pins XL1/2 are activated automatically and
this bit is reset. With any change of this bit an interrupt
ISR1.XLSC is generated. In case of XPM2.XLT is set this bit is
frozen.
This bit is set if at least 32 consecutive zeros were sent on pins
XL1/XL2 or XDOP/XDON. This bit is reset with the first
transmitted pulse. With the rising edge of this bit an interrupt
ISR1.XLSC is set. In case of XPM2.XLT is set this bit is frozen.
431
-3
DS1.1, 2003-10-23
T1/J1 Registers
PEF 2256 H/E
. A data stream
FALC
®
56