PEF2256 INFINEON [Infineon Technologies AG], PEF2256 Datasheet - Page 433

• Manufacturer Part Number: PEF2256
• Description: E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

Some of these alarm indications are simulated only if the FALC
appropriate mode. At simulation steps 0, 3, 4, and 7 pending status flags are reset
automatically and clearing of the error counters and interrupt status registers ISR(5:0)
should be done. Incrementing the simulation counter should not be done at time intervals
shorter than 1.5 ms (F4, F12, F72) or 3 ms (ESF). Otherwise, reactions of initiated
simulations might occur at later steps. Control bit FMR0.SIM has to be held stable at high
or low level for at least one receive clock period before changing it again.
Framing Error Counter (Read)
FECL
FECH
FE(15:0)
User’s Manual
Hardware Description
FE15
FE7
7
7
Framing Errors
This 16-bit counter is incremented when incorrect FT and FS-bits in
F4, F12 and F72 format or incorrect FAS-bits in ESF format are
received.
Framing errors are counted during synchronous state only (but even
if multiframe synchronous state is not reached yet). The error counter
does not roll over.
During alarm simulation, the counter is incremented twice.
Clearing and updating the counter is done according to bit
FMR1.ECM.
If this bit is reset the error counter is permanently updated in the
buffer. For correct read access of the error counter bit DEC.DFEC has
to be set. With the rising edge of this bit updating the buffer is stopped
and the error counter is reset. Bit DEC.DFEC is automatically reset
with reading the error counter high byte.
If FMR1.ECM is set every second (interrupt ISR3.SEC) the error
counter is latched and then automatically reset. The latched error
counter state should be read within the next second.
433
®
56 is configured in the
DS1.1, 2003-10-23
T1/J1 Registers
PEF 2256 H/E
FE0
FE8
0
0
FALC
(50)
(51)
®
56