PEF2256 INFINEON [Infineon Technologies AG], PEF2256 Datasheet - Page 387

• Manufacturer Part Number: PEF2256
• Description: E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

ELT
MPAS
LOS1
Loop Code Register 1 (Read/Write)
Value after reset: 00
LCR1
EPRM
User’s Manual
Hardware Description
EPRM
7
XPRBS
Enable Loop-Timed
0 =
1 =
Multi-Purpose Analog Switch
This bit controls the analog switch between pins AS1 and AS2.
0 =
1 =
Loss-of-Signal Recovery condition
0 =
1 =
Enable Pseudo-Random Binary Sequence Monitor
0 =
1 =
H
Transmit clock is generated from the clock supplied by MCLK
which is synchronized to the extracted receive route clock. In
this configuration the transmit elastic buffer has to be enabled.
Refer to register FMR5.XTM. For correct operation of loop
timed the remote loop (bit LIM1.RL = 0) must be inactive and bit
CMR1.DXSS must be cleared.
Normal operation
Switch is open.
Switch is closed.
The LOS alarm is cleared if the predefined pulse-density
(register PCR) is detected during the time interval which is
defined by register PCD.
Additionally to the recovery condition described above a LOS
alarm is only cleared if the pulse-density is fulfilled and no more
than 15 contiguous zeros are detected during the recovery
interval (according to GR-499-CORE).
Pseudo-random binary sequence (PRBS) monitor is disabled.
PRBS is enabled. Setting this bit enables incrementing the bit
error counter BEC with each detected PRBS bit error. With any
change of state of the PRBS internal synchronization status an
interrupt ISR3.LLBSC is generated. The current status of the
PRBS synchronizer is indicated by bit FRS1.LLBAD.
LDC1
LDC0
387
LAC1
LAC0
FLLB
DS1.1, 2003-10-23
T1/J1 Registers
PEF 2256 H/E
LLBP
0
FALC
(3B)
®
56