PEF2256 INFINEON [Infineon Technologies AG], PEF2256 Datasheet - Page 384

• Manufacturer Part Number: PEF2256
• Description: E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

JATT, RL
DRS
Pulse Count Detection Register (Read/Write)
Value after reset: 00
PCD
PCD(7:0)
User’s Manual
Hardware Description
PCD7
7
Pulse Count Detection
Remote Loop Transmit Jitter Attenuator
00 = Normal operation. The remote loop transmit jitter attenuator is
01 = Remote Loop active without transmit jitter attenuator enabled.
10 = not assigned
11 = Remote Loop and remote loop jitter attenuator active. Received
Note:JATT is only used to define the jitter attenuation during remote
0 =
1 =
A LOS alarm (red alarm) is detected if the incoming data stream has
no transitions for a programmable number T consecutive pulse
positions. The number T is programmable by the PCD register and
can be calculated as follows:
T = 16
The maximum time is: 256
pulse resets the internal pulse counter. The counter is clocked with
the receive clock RCLK.
Dual-Rail Select
H
disabled. Transmit data bypasses the remote loop jitter
attenuator buffer.
Transmit data bypasses the remote loop jitter attenuator buffer.
data from pins RL1/2 or RDIP/N or ROID is sent "jitter-free" on
ports XL1/2 or XDOP/N or XOID. The de-jittered clock is
generated by the DCO-X circuitry.
The ternary interface is selected. Multifunction ports RL1/2 and
XL1/2 become analog in/outputs.
The digital dual-rail interface is selected. Received data is
latched on multifunction ports RDIP/RDIN while transmit data is
output on pins XDOP/XDON.
loop operation. Jitter attenuation during normal operation is
not affected.
(N+1); with 0 N 255.
384
16
648 ns = 2.65 ms. Every detected
DS1.1, 2003-10-23
T1/J1 Registers
PEF 2256 H/E
PCD0
0
FALC
(38)
®
56