PEF2256 INFINEON [Infineon Technologies AG], PEF2256 Datasheet - Page 364

• Manufacturer Part Number: PEF2256
• Description: E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

Framer Mode Register 2 (Read/Write)
Value after reset: 00
FMR2
AFRS
MCSP
SSP
User’s Manual
Hardware Description
AFRS
7
Automatic Force resynchronization
0 =
1 =
Multiple Candidates Synchronization Procedure
Select Synchronization/Resynchronization Procedure
Together with bit FMR2.SSP the synchronization mode of the receive
framer is defined:
MCSP/SSP:
00 = F12/F72 format:
Specified number of errors in both FT framing and FS framing lead to
loss of sync (FRS0.LFA is set). In the case of FS-bit framing errors,
bit FRS0.LMFA is set additionally. A complete new synchronization
procedure is initiated to regain pulseframe alignment and then
multiframe alignment.
F24:
normal operation: synchronization is achieved only on verification the
framing pattern.
01 = F12/F72:
Specified number of errors in FT framing has the same effect as
above. Specified number of errors in FS framing only initiates a new
search for multiframe alignment without influencing pulseframe
synchronous state (FRS0.LMFA is set).
F24:
Synchronous state is reached when three consecutive multiframe
pattern are correctly found independent of the occurrence of CRC6
errors.
10 = F12/F24:
A one enables a synchronization mode which is able to choose
multiple framing pattern candidates step by step. I.e. if in synchronous
state the CRC error counter indicates that the synchronization might
MCSP
H
Default operation, no automatic search in case of multiple
framing candidates.
Search for next framing candidate automatically, if multiple
candidates are present and the current candidate is incorrect.
SSP
DAIS
364
SAIS
PLB
AXRA
DS1.1, 2003-10-23
T1/J1 Registers
PEF 2256 H/E
EXZE
0
FALC
(1E)
®
56