PEF2256 INFINEON [Infineon Technologies AG], PEF2256 Datasheet - Page 376

• Manufacturer Part Number: PEF2256
• Description: E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

User’s Manual
Hardware Description
Receive Frame Marker Offset (PC(4:1).RPC(2:0) = 001
Offset programming of the receive frame marker which is output on
multifunction port RFM. The receive frame marker can be activated
during any bit position of the entire frame and depends on the
selected system clock rate.
Calculation of the value X of the receive offset register RC(1:0)
depends on the bit position which should be marked at marker
position MP:
system clocking rate: modulo 2.048 MHz (SIC2.SSC2 = 0)
0 MP
2046 MP 2047:X = MP - 2046)
e.g: 2.048 MHz: MP = 0 to 255; 4.096 MHz: MP = 0 to 511,
8.192 MHz: MP = 0 to 1023, 16.384 MHz: MP = 0 to 2047
system clocking rate: modulo 1.544 MHz (SIC2.SSC2 = 1)
0 MP 193
193
X = MP + 2 - 186
with maximum delay = 193 SC/SD - 1
with SC = system clock defined by SIC1.SSC(1:0)+SIC2.SSC2
with SD = system data rate
(SC/SD) -2 MP maximum delay:
2045:X = MP + 2
(SC/SD) - 3:X = MP + 2 + 7
SC/SD
376
SC/SD
DS1.1, 2003-10-23
T1/J1 Registers
PEF 2256 H/E
B
FALC
)
®
56